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AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT89LP216-20PU

MICROCHIPID: C20929377PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL · 16 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL)1P15 .2P17 .3P13 .4GND5P12 .6P30 .7P34 .8P32 .16P16 .15P14 .14P11 .13P10 .12VDD11P31 .10P35 .9P33 .Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.815.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
12345678910111213141516E=6.35mm · Pitch e=2.54mmD=19.78mm-10-8-6-4-2024681015131197531-1-3-5-7-9-11-13-15mm
3. 3D CAD MODEL
Package Body: 6.35mm × 19.78mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (16/16)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P15 .I/OMultiplexed I/O & Peripheral Pin P15 . (SPI)
2P17 .I/OMultiplexed I/O & Peripheral Pin P17 . (SPI)
3P13 .I/OMultiplexed I/O & Peripheral Pin P13 . (General)
4GNDGNDGround Reference Pin (GND)
5P12 .I/OMultiplexed I/O & Peripheral Pin P12 . (General)
6P30 .I/OMultiplexed I/O & Peripheral Pin P30 . (UART)
7P34 .I/OMultiplexed I/O & Peripheral Pin P34 . (General)
8P32 .I/OMultiplexed I/O & Peripheral Pin P32 . (RTC/CLK)
9P33 .I/OMultiplexed I/O & Peripheral Pin P33 . (RTC/CLK)
10P35 .I/OMultiplexed I/O & Peripheral Pin P35 . (General)
11P31 .I/OMultiplexed I/O & Peripheral Pin P31 . (UART)
12VDDPowerPower Supply Input (VDD — 2.4V to 5.5V)
13P10 .I/OMultiplexed I/O & Peripheral Pin P10 . (ADC)
14P11 .I/OMultiplexed I/O & Peripheral Pin P11 . (ADC)
15P14 .I/OMultiplexed I/O & Peripheral Pin P14 . (SPI)
16P16 .I/OMultiplexed I/O & Peripheral Pin P16 . (SPI)
PIN 1 P15 .
I/O
Multiplexed I/O & Peripheral Pin P15 . (SPI)
Design note: P1 .5: User-configurable I/O Port 1 bit 5 . MOSI: SPI master-out/slave-in When configured as master this pin is an output When configured as slave this pin . , . , isaninput . GPI5: General -purpose Interrupt input 5 .
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT89LP216-20PU (MICROCHIP · PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) - 2. Standard Pinout (Top View)
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) - 4. Package Dimensions (D×E×A)
PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL · 6.35×19.78mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) - 5. Recommended Land Pattern
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for AT89LP216
P1 · p01_fig01652×376px
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) — 8-bit Microcontroller with 2K Bytes Flash
8-bit Microcontroller with 2K Bytes Flash
P2 · p02_fig01P2
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P90 · p90_fig012124×2562px
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) — 90 | 3621E-MICRO-11/10 AT89LP216 | 27. Packaging Information | 27.1 16P3 - PDIP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 16P3, 16-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) A 16P3 | 11/02/0
90 | 3621E-MICRO-11/10 AT89LP216 | 27. Packaging Information | 27.1 16P3 - PDIP | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 16P3, 16-lead (0.300"/7.62 mm Wide) Plastic Dual Inline Package (PDIP) A 16P3 | 11/02/0
P90 · p90_fig01P90
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) — Datasheet Page 90 (p90_fig01)
Datasheet Page 90 (p90_fig01)
P2 · p02_fig01All Packages in PDF
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) — 2. Pin Configuration
2. Pin Configuration
P91 · p91_fig01All Packages in PDF
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) — 91 | 3621E-MICRO-11/10 | AT89LP216 | 27.2 16S - SOIC | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 16S, 16-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) | 11/02/05 | 16S A | A1 | E | L | S
91 | 3621E-MICRO-11/10 | AT89LP216 | 27.2 16S - SOIC | 2325 Orchard Parkway San Jose, CA 95131 | TITLE DRAWING NO. | R | REV. 16S, 16-lead, 0.300" Wide Body, Plastic Gull Wing Small Outline Package (SOIC) | 11/02/05 | 16S A | A1 | E | L | S
P92 · p92_fig01All Packages in PDF
AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) — 92 | 3621E-MICRO-11/10 AT89LP216 | 27.3 16X - TSSOP | TITLE DRAWING NO. | R | REV. 2325 Orchard Parkway San Jose, CA 95131 | 11/11/05 | 16X, 16-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) 16X A | COMMON DIMENS
92 | 3621E-MICRO-11/10 AT89LP216 | 27.3 16X - TSSOP | TITLE DRAWING NO. | R | REV. 2325 Orchard Parkway San Jose, CA 95131 | 11/11/05 | 16X, 16-lead, 4.4 mm Body Width, Plastic Thin Shrink Small Outline Package (TSSOP) 16X A | COMMON DIMENS

Technical Specifications & Part Details (AT89LP216-20PU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) is a 16-pin standard electronic & interconnect component featuring a 19.78 × 6.35 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 2.4V to 5.5V supply operation across -40°C to +85°C with integrated UART, SPI, PWM, ADC, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.4V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
19.78 × 6.35 × 4.20 mm (A1=0.51 mm)
Package family: DIP (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, PWM, ADC, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol16 auto-grouped pins
OK
IPC-7351B Land Pattern16 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
19.78 × 6.35 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
16P / 16Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL)?

Manufactured by MICROCHIP, the AT89LP216-20PU is housed in a PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL package with 16 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 2.4V to 5.5V. Key pins include: 1 (P15 .: Multiplexed I/O & Peripheral Pin P15 . (SPI)), 2 (P17 .: Multiplexed I/O & Peripheral Pin P17 . (SPI)), 3 (P13 .: Multiplexed I/O & Peripheral Pin P13 . (General)), 4 (GND: Ground Reference Pin (GND)), 5 (P12 .: Multiplexed I/O & Peripheral Pin P12 . (General)), 6 (P30 .: Multiplexed I/O & Peripheral Pin P30 . (UART)).

What are the IPC-7351B PCB Footprint dimensions for AT89LP216-20PU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT89LP216-20PU (PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) has a nominal body envelope of 6.35 × 19.78 mm, pitch e = 2.54 mm, and 16 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT89LP216-20PU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT89LP216-20PU (MICROCHIP, PDIP-16_L19.7-W6.6-P2.54-LS7.6-BL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (16 pins) & AT89LP216 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P15 .Digital_IOSignal terminal P15 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
2P17 .Digital_IOSignal terminal P17 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: SPICLOCK. Supported peripheral buses: SPI.
3P13 .Digital_IOSignal terminal P13 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P13 .. Supported peripheral buses: General.
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5P12 .Digital_IOSignal terminal P12 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P12 .. Supported peripheral buses: General.
6P30 .Digital_IOSignal terminal P30 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P30 .. Supported peripheral buses: UART.
7P34 .Digital_IOSignal terminal P34 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P34 .. Supported peripheral buses: General.
8P32 .Digital_IOSignal terminal P32 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P32 .. Supported peripheral buses: RTC/CLK.
9P33 .Digital_IOSignal terminal P33 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P33 .. Supported peripheral buses: RTC/CLK.
10P35 .Digital_IOSignal terminal P35 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P35 .. Supported peripheral buses: General.
11P31 .Digital_IOSignal terminal P31 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P31 .. Supported peripheral buses: UART.
12VDDPower_InPrimary positive power supply input (VDD) operating in the 2.4V to 5.5V domain (Max rating: 5.5V).
13P10 .Digital_IOSignal terminal P10 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P10 .. Supported peripheral buses: ADC.
14P11 .Digital_IOSignal terminal P11 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: P11 .. Supported peripheral buses: ADC.
15P14 .Digital_IOSignal terminal P14 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: SPISLAVESELECTINPUT. Supported peripheral buses: SPI.
16P16 .Digital_IOSignal terminal P16 . (I/O, 2.4V to 5.5V domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
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