Mechanical Dimensions & Land Pattern (QFN-12(2x2))
Extracted from Datasheet & IPC-7351B NormalizedRecommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-12(2x2) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — LX7180A-31CLQ-TR (QFN-12(2x2))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of LX7180A-31CLQ-TR (QFN-12(2x2))?
Manufactured by MICROCHIP, the LX7180A-31CLQ-TR is housed in a QFN-12(2x2) package with 12 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 3.0 V - 5.5 V. Key pins include: 1 (PVIN: Power Supply Input (PVIN — 3.0 V - 5.5 V)), 2 (SW: Multiplexed I/O & Peripheral Pin SW (General)), 3 (PGND: Ground Reference Pin (PGND)), 4 (AGND: Ground Reference Pin (AGND)), 5 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)), 6 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)).
What are the IPC-7351B PCB Footprint dimensions for LX7180A-31CLQ-TR?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), LX7180A-31CLQ-TR (QFN-12(2x2)) has a nominal body envelope of 2.00 × 2.00 mm, pitch e = 0.50 mm, and 12 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for LX7180A-31CLQ-TR?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for LX7180A-31CLQ-TR (MICROCHIP, QFN-12(2x2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (12 pins) & LX7180 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PVIN | Power_In | Primary positive power supply input (PVIN) operating in the 3.0 V - 5.5 V domain (Max rating: 5.5V). |
| 2 | SW | Digital_IO | Signal terminal SW (I/O, 3.0 V - 5.5 V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General. |
| 3 | PGND | GND | 0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | AGND | GND | 0V electrical ground return terminal (AGND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 5 | SCL | Digital_IO | Signal terminal SCL (I/O, 3.0 V - 5.5 V domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C. |
| 6 | SDA | Digital_IO | Signal terminal SDA (I/O, 3.0 V - 5.5 V domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C. |
| 7 | FB | Digital_IO | Signal terminal FB (I/O, 3.0 V - 5.5 V domain). Multiplexed alternate functions: FB. Supported peripheral buses: General. |
| 8 | EN | Digital_IO | Chip enable and power-on reset control input (EN): High enables the SoC; Low powers down the chip into reset. |
| 9 | PG | Open_Drain | Signal terminal PG (I/O, 3.0 V - 5.5 V domain). Multiplexed alternate functions: PG. Supported peripheral buses: General. |
| 10 | PVIN | Power_In | Primary positive power supply input (PVIN) operating in the 3.0 V - 5.5 V domain (Max rating: 5.5V). |
| 11 | SW | Digital_IO | Signal terminal SW (I/O, 3.0 V - 5.5 V domain). Multiplexed alternate functions: SW. Supported peripheral buses: General. |
| 12 | PGND | GND | 0V electrical ground return terminal (PGND) for internal core logic, I/O drivers, and analog sub-blocks. |