QFN-20(3x3) · 21P
Synchronized Pinout (Symbol / 2D / 3D) (21/21)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (General) |
| 2 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| 3 | VDCID | I/O | Multiplexed I/O & Peripheral Pin VDCID (General) |
| 4 | VSW | I/O | Multiplexed I/O & Peripheral Pin VSW (General) |
| 5 | VIO33/VDD33 | Power | Power Supply Input (VIO33/VDD33 — 3.3V / 5.0V Standard Logic) |
| 6 | RB PIN_USBDPPU___ | I/O | Multiplexed I/O & Peripheral Pin RB PIN_USBDPPU___ (USB) |
| 7 | RB_PINUSBIE__ | I/O | Multiplexed I/O & Peripheral Pin RB_PINUSBIE__ (USB) |
| 8 | PB11/UD+/TMR2_ | I/O | Multiplexed I/O & Peripheral Pin PB11/UD+/TMR2_ (USB) |
| 9 | PB10/UD-/TMR1_ | I/O | Multiplexed I/O & Peripheral Pin PB10/UD-/TMR1_ (USB) |
| 10 | PB7/TXD0/PWM9 | I/O | Multiplexed I/O & Peripheral Pin PB7/TXD0/PWM9 (UART, PWM) |
| 11 | PB4/RXD0/PWM7 | I/O | Multiplexed I/O & Peripheral Pin PB4/RXD0/PWM7 (UART, PWM) |
| 12 | X32MO | I/O | Multiplexed I/O & Peripheral Pin X32MO (General) |
| 13 | X32MI | I/O | Multiplexed I/O & Peripheral Pin X32MI (General) |
| 14 | VINTA | Power | Power Supply Input (VINTA — 3.3V / 5.0V Standard Logic) |
| 15 | ANT | I/O | Multiplexed I/O & Peripheral Pin ANT (General) |
| 16 | VDCIA | I/O | Multiplexed I/O & Peripheral Pin VDCIA (General) |
| 17 | PA15/MISO/RXD0_/AIN5 | I/O | Multiplexed I/O & Peripheral Pin PA15/MISO/RXD0_/AIN5 (UART, SPI, ADC) |
| 18 | PA14/MOSI/TXD0_/AIN4 | I/O | Multiplexed I/O & Peripheral Pin PA14/MOSI/TXD0_/AIN4 (UART, SPI, ADC) |
| 19 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (SPI, PWM) |
| 20 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (SPI, PWM) |
| 21 | GND | GND | Ground Reference Pin (GND) |
PIN 1 PA11
I/OMultiplexed I/O & Peripheral Pin PA11 (General)
Design note: connectedtotheendofexternal32KHzcrystal . TMR2: Capture input 2 andPWM output channel 2 of timer | Alt: /TMR2
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-20(3x3) · 3.00×3.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH591 / CH592
P154 · p154_fig01EXACT PACKAGE
P1 · p01_fig01279×170px
P3 · p03_fig011715×1991px
P55 · p55_fig011830×1886px
P55 · p55_fig01P55
P154 · p154_fig021200×1075px
P153 · p153_fig01All Packages in PDF
P153 · p153_fig02All Packages in PDF
Technical Specifications & Part Details (CH591D)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH591D (QFN-20(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Bluetooth / BLE, USB, UART, SPI, I2C, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-20(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Bluetooth / BLE, USB, UART, SPI, I2C, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol21 auto-grouped pins
IPC-7351B Land Pattern21 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteEPAD 1.65×1.65mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH591 / CH592 (5)
QFN-20(3x3) · 21P
QFN-28(4x4) · 29P
QFN-28-EP(4x4) · 29P
QFN-32-EP(4x4) · 33P
Mechanical Dimensions & Land Pattern (QFN-20(3x3))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-20(3x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH591D (QFN-20(3x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH591D (QFN-20(3x3))?
Manufactured by WCH, the CH591D is housed in a QFN-20(3x3) package with 21 pins and a 0.50 mm lead pitch. Key pins include: 1 (PA11: Multiplexed I/O & Peripheral Pin PA11 (General)), 2 (PA10: Multiplexed I/O & Peripheral Pin PA10 (General)), 3 (VDCID: Multiplexed I/O & Peripheral Pin VDCID (General)), 4 (VSW: Multiplexed I/O & Peripheral Pin VSW (General)), 5 (VIO33/VDD33: Power Supply Input (VIO33/VDD33 — 3.3V / 5.0V Standard Logic)), 6 (RB PIN_USBDPPU___: Multiplexed I/O & Peripheral Pin RB PIN_USBDPPU___ (USB)).
What are the IPC-7351B PCB Footprint dimensions for CH591D?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH591D (QFN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.50 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.65 × 1.65 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH591D?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH591D (WCH, QFN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (21 pins) & CH591 / CH592 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General. |
| 2 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General. |
| 3 | VDCID | Digital_IO | Signal terminal VDCID (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCID. Supported peripheral buses: General. |
| 4 | VSW | Digital_IO | Signal terminal VSW (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VSW. Supported peripheral buses: General. |
| 5 | VIO33/VDD33 | Power_In | Primary positive power supply input (VIO33/VDD33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 6 | RB PIN_USBDPPU___ | Digital_IO | Signal terminal RB PIN_USBDPPU___ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB PIN_USBDPPU___. Supported peripheral buses: USB. |
| 7 | RB_PINUSBIE__ | Digital_IO | Signal terminal RB_PINUSBIE__ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RB_PINUSBIE__. Supported peripheral buses: USB. |
| 8 | PB11/UD+/TMR2_ | Digital_IO | Signal terminal PB11/UD+/TMR2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11/UD+/TMR2_. Supported peripheral buses: USB. |
| 9 | PB10/UD-/TMR1_ | Digital_IO | Signal terminal PB10/UD-/TMR1_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10/UD-/TMR1_. Supported peripheral buses: USB. |
| 10 | PB7/TXD0/PWM9 | Digital_IO | Signal terminal PB7/TXD0/PWM9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/TXD0/PWM9. Supported peripheral buses: UART, PWM. |
| 11 | PB4/RXD0/PWM7 | Digital_IO | Signal terminal PB4/RXD0/PWM7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4/RXD0/PWM7. Supported peripheral buses: UART, PWM. |
| 12 | X32MO | Digital_IO | Signal terminal X32MO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MO. Supported peripheral buses: General. |
| 13 | X32MI | Digital_IO | Signal terminal X32MI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: X32MI. Supported peripheral buses: General. |
| 14 | VINTA | Power_In | Primary positive power supply input (VINTA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 15 | ANT | RF_50Ohm | Signal terminal ANT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ANT. Supported peripheral buses: General. |
| 16 | VDCIA | Digital_IO | Signal terminal VDCIA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VDCIA. Supported peripheral buses: General. |
| 17 | PA15/MISO/RXD0_/AIN5 | Digital_IO | Signal terminal PA15/MISO/RXD0_/AIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI, ADC. |
| 18 | PA14/MOSI/TXD0_/AIN4 | Digital_IO | Signal terminal PA14/MOSI/TXD0_/AIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI, ADC. |
| 19 | PA13 | Digital_IO | Signal terminal PA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI0SERIALCLOCKPIN. Supported peripheral buses: SPI, PWM. |
| 20 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI0CHIPSELECTINPUTINSLAVEMODE. Supported peripheral buses: SPI, PWM. |
| 21 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |