ChipDocs.org
⌘K
2284 PARTSUpload PDF
STM32F038E6Y6TR (WLCSP-25) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F038E6Y6TR

STID: C2054179WLCSP-25 · 25 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F038E6Y6TR (WLCSP-25)A1PA13 (SWDIO)A2PA14 (SWCLK)A3PB7A4BOOT0A5PF0OSC IN -_B1PA10B2PB6B3PA4B4PA0B5PF1OSC OUT -C1PA9C2PB5C3PA5E5PA3E4PA7E3PB0E2NPORE1VSSD5VDDAD4PA2D3PA6D2PA8D1VDDC5NRSTC4PA1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
A1B1C1D1E1A2B2C2D2E2A3B3C3D3E3A4B4C4D4E4A5B5C5D5E5E=2.40mm · Pitch e=0.40mmD=2.30mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 2.40mm × 2.30mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (25/25)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PA13 (SWDIO)I/OMultiplexed I/O & Peripheral Pin PA13 (SWDIO) (SWD/JTAG)
A2PA14 (SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (SWCLK) (UART, SWD/JTAG)
A3PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
A4BOOT0IInput-Only Pin BOOT0 (General)
A5PF0OSC IN -_ (PF0)I/OMultiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (RTC/CLK)
B1PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, I2C, PWM)
B2PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC)
B4PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, ADC, PWM, RTC/CLK)
B5PF1OSC OUT -_ (PF1)I/OMultiplexed I/O & Peripheral Pin PF1OSC OUT -_ (PF1) (RTC/CLK)
C1PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, PWM)
C2PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM)
C3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
C4PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
C5NRSTISystem Enable & Hardware Reset (NRST)
D1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D2PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, PWM, RTC/CLK)
D3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
D4PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
D5VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
E1VSSGNDGround Reference Pin (VSS)
E2NPORI/OMultiplexed I/O & Peripheral Pin NPOR (General)
E3PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
E4PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
E5PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
PIN A1 PA13 (SWDIO)
I/O
Multiplexed I/O & Peripheral Pin PA13 (SWDIO) (SWD/JTAG)
Design note: Alt: IR_OUT , SWDIO
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 27 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F038E6Y6TR (ST · WLCSP-25)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F038E6Y6TR (WLCSP-25) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F038E6Y6TR (WLCSP-25) - 2. Standard Pinout (Top View)
True package pinout (25 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F038E6Y6TR (WLCSP-25) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F038E6Y6TR (WLCSP-25) - 4. Package Dimensions (D×E×A)
WLCSP-25 · 2.40×2.30mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F038E6Y6TR (WLCSP-25) - 5. Recommended Land Pattern
IPC-7351B Footprint (25 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F038E6Y6TR (WLCSP-25) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (27 figures · Page 1/3)
Showing 1–12 of 27 uncropped original figures for STM32F038
P1 · p01_fig02EXACT PACKAGE
STM32F038E6Y6TR (WLCSP-25) — • All packages ECOPACK®2
• All packages ECOPACK®2
P24 · p24_fig01EXACT PACKAGE
STM32F038E6Y6TR (WLCSP-25) — Figure 5. UFQFPN28 package pinout
Figure 5. UFQFPN28 package pinout
P24 · p24_fig02EXACT PACKAGE
STM32F038E6Y6TR (WLCSP-25) — Figure 6. WLCSP25 package pinout
Figure 6. WLCSP25 package pinout
P26 · p26_fig01EXACT PACKAGE
STM32F038E6Y6TR (WLCSP-25) — 26/102 DocID026079 Rev 5
26/102 DocID026079 Rev 5
P89 · p89_fig01EXACT PACKAGE
STM32F038E6Y6TR (WLCSP-25) — Figure 39. WLCSP25 package outline H ) *
Figure 39. WLCSP25 package outline H ) *
P90 · p90_fig01EXACT PACKAGE
STM32F038E6Y6TR (WLCSP-25) — Figure 40. Recommended footprint for WLCSP25 package
Figure 40. Recommended footprint for WLCSP25 package
P100 · p100_fig01EXACT PACKAGE
STM32F038E6Y6TR (WLCSP-25) — Revision history STM32F038x6
Revision history STM32F038x6
P1 · p01_fig011126×502px
STM32F038E6Y6TR (WLCSP-25) — • Power management - Digital and I/Os supply: VDD = 1.8 V ±8% - Analog supply: VDDA = from VDD to 3.6 V - Low power modes: Sleep, Stop - VBAT supply for RTC and backup registers
• Power management - Digital and I/Os supply: VDD = 1.8 V ±8% - Analog supply: VDDA = from VDD to 3.6 V - Low power modes: Sleep, Stop - VBAT supply for RTC and backup registers
P37 · p37_fig011546×1319px
STM32F038E6Y6TR (WLCSP-25) — Figure 11. Power supply scheme
Figure 11. Power supply scheme
P37 · p37_fig01P37
STM32F038E6Y6TR (WLCSP-25) — Datasheet Page 37 (p37_fig01)
Datasheet Page 37 (p37_fig01)
P55 · p55_fig011546×718px
STM32F038E6Y6TR (WLCSP-25) — Figure 15. Typical application with an 8 MHz crystal
Figure 15. Typical application with an 8 MHz crystal
P72 · p72_fig011751×902px
STM32F038E6Y6TR (WLCSP-25) — Figure 23. ADC accuracy characteristics
Figure 23. ADC accuracy characteristics
Page 1 / 3 (27 extracted figures)

Technical Specifications & Part Details (STM32F038E6Y6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F038E6Y6TR (WLCSP-25) is a 25-pin embedded microcontroller unit (mcu) featuring a 2.30 × 2.40 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
10 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
2.30 × 2.40 × 0.56 mm (A1=0.17 mm)
Package family: WLCSP (WLCSP-25)
Pin Count & Lead PitchN / e
25 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol25 auto-grouped pins
OK
IPC-7351B Land Pattern25 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32F038 (4)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (WLCSP-25)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
2.30 × 2.40 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
25P / 25Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-25
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F038E6Y6TR (WLCSP-25)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F038E6Y6TR (WLCSP-25)?

Manufactured by ST, the STM32F038E6Y6TR is housed in a WLCSP-25 package with 25 pins and a 0.40 mm lead pitch. Key pins include: A1 (PA13 (SWDIO): Multiplexed I/O & Peripheral Pin PA13 (SWDIO) (SWD/JTAG)), A2 (PA14 (SWCLK): Multiplexed I/O & Peripheral Pin PA14 (SWCLK) (UART, SWD/JTAG)), A3 (PB7: Multiplexed I/O & Peripheral Pin PB7 (UART, I2C)), A4 (BOOT0: Input-Only Pin BOOT0 (General)), A5 (PF0OSC IN -_ (PF0): Multiplexed I/O & Peripheral Pin PF0OSC IN -_ (PF0) (RTC/CLK)), B1 (PA10: Multiplexed I/O & Peripheral Pin PA10 (UART, I2C, PWM)).

What are the IPC-7351B PCB Footprint dimensions for STM32F038E6Y6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F038E6Y6TR (WLCSP-25) has a nominal body envelope of 2.40 × 2.30 mm, pitch e = 0.40 mm, and 25 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F038E6Y6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F038E6Y6TR (ST, WLCSP-25) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (25 pins) & STM32F038 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PA13 (SWDIO)Digital_IOSignal terminal PA13 (SWDIO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (SWDIO). Supported peripheral buses: SWD/JTAG.
A2PA14 (SWCLK)Digital_IOSignal terminal PA14 (SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (SWCLK). Supported peripheral buses: UART, SWD/JTAG.
A3PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
A4BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A5PF0OSC IN -_ (PF0)Digital_IOSignal terminal PF0OSC IN -_ (PF0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF0OSC IN -_ (PF0). Supported peripheral buses: RTC/CLK.
B1PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C, PWM.
B2PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
B3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC.
B4PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
B5PF1OSC OUT -_ (PF1)Digital_IOSignal terminal PF1OSC OUT -_ (PF1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF1OSC OUT -_ (PF1). Supported peripheral buses: RTC/CLK.
C1PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, PWM.
C2PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, I2C1_SMBA. Supported peripheral buses: SPI, I2C, PWM.
C3PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
C4PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
C5NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
D1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D2PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, PWM, RTC/CLK.
D3PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC, PWM.
D4PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
D5VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E2NPORDigital_IOSignal terminal NPOR (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: NPOR. Supported peripheral buses: General.
E3PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
E4PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
E5PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
ExplorePartsPackagesMFRsUpload