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CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) — Symbol, Footprint IPC-7351B & 3D STEP Model

CRT9006-83HSBIP

MICROCHIPID: C20537916PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL · 24 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL)1DOUT32DOUT23DOUT14DOUT05CLK6WREN#7CLRCNT#8CKEN9DIN010DIN111DIN212DIN324GND23DOUT422DOUT521DOUT620DOUT719OE#18OF17DIN716DIN615DIN514DIN413+5VGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.820.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324E=13.70mm · Pitch e=2.54mmD=29.94mm-16-14-12-10-8-6-4-202468101214162321191715131197531-1-3-5-7-9-11-13-15-17-19-21-23mm
3. 3D CAD MODEL
Package Body: 13.70mm × 29.94mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (24/24)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DOUT3I/OMultiplexed I/O & Peripheral Pin DOUT3 (General)
2DOUT2I/OMultiplexed I/O & Peripheral Pin DOUT2 (General)
3DOUT1I/OMultiplexed I/O & Peripheral Pin DOUT1 (General)
4DOUT0I/OMultiplexed I/O & Peripheral Pin DOUT0 (General)
5CLKI/OMultiplexed I/O & Peripheral Pin CLK (General)
6WREN#I/OMultiplexed I/O & Peripheral Pin WREN# (General)
7CLRCNT#I/OMultiplexed I/O & Peripheral Pin CLRCNT# (General)
8CKENI/OMultiplexed I/O & Peripheral Pin CKEN (General)
9DIN0I/OMultiplexed I/O & Peripheral Pin DIN0 (General)
10DIN1I/OMultiplexed I/O & Peripheral Pin DIN1 (General)
11DIN2I/OMultiplexed I/O & Peripheral Pin DIN2 (General)
12DIN3I/OMultiplexed I/O & Peripheral Pin DIN3 (General)
13+5VPowerPower Supply Input (+5V — 3.3V / 5.0V Standard Logic)
14DIN4I/OMultiplexed I/O & Peripheral Pin DIN4 (General)
15DIN5I/OMultiplexed I/O & Peripheral Pin DIN5 (General)
16DIN6I/OMultiplexed I/O & Peripheral Pin DIN6 (General)
17DIN7I/OMultiplexed I/O & Peripheral Pin DIN7 (General)
18OFI/OMultiplexed I/O & Peripheral Pin OF (General)
19OE#I/OMultiplexed I/O & Peripheral Pin OE# (General)
20DOUT7I/OMultiplexed I/O & Peripheral Pin DOUT7 (General)
21DOUT6I/OMultiplexed I/O & Peripheral Pin DOUT6 (General)
22DOUT5I/OMultiplexed I/O & Peripheral Pin DOUT5 (General)
23DOUT4I/OMultiplexed I/O & Peripheral Pin DOUT4 (General)
24GNDGNDGround Reference Pin (GND)
PIN 1 DOUT3
I/O
Multiplexed I/O & Peripheral Pin DOUT3 (General)
Design note: Signal terminal DOUT3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT3. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CRT9006-83HSBIP (MICROCHIP · PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) - 2. Standard Pinout (Top View)
True package pinout (24 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) - 4. Package Dimensions (D×E×A)
PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL · 13.70×29.94mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) - 5. Recommended Land Pattern
IPC-7351B Footprint (24 Pads)Expand ›
6. Application SchematicSCHEMATIC
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CRT9006
P1 · p01_fig011803×2302px
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) — Single Row Buffer FEATURES: PIN CONFIGURATION OC Low Cost Solution to CRT Memory Contention Problem CO Provides Enhanced Processor Throughput for CRT courts C}1 24) GND Display Systems voutz C2 235) pouts O Provides 8 Bit Wide Variable Leng
Single Row Buffer FEATURES: PIN CONFIGURATION OC Low Cost Solution to CRT Memory Contention Problem CO Provides Enhanced Processor Throughput for CRT courts C}1 24) GND Display Systems voutz C2 235) pouts O Provides 8 Bit Wide Variable Leng
P2 · p02_fig011803×2302px
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) — DESCRIPTION OF PIN FUNCTIONS = DATA OUTPUTS DOUT3-DOUT® | Data Outputs from the internal output latch. cLock CLK Character clock. The negative-going edge of CLK clocks the latches. When CKEN (pin 8) is high, CLK will increment the address c
DESCRIPTION OF PIN FUNCTIONS = DATA OUTPUTS DOUT3-DOUT® | Data Outputs from the internal output latch. cLock CLK Character clock. The negative-going edge of CLK clocks the latches. When CKEN (pin 8) is high, CLK will increment the address c
P2 · p02_fig01P2
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P4 · p04_fig011803×2302px
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) — FIGURE 1: AC CHARACTERISTICS -_——, —__ ee ten pl oe cux i tb ow TDR LB /T/L, | twcro—*] ant tence ~ Nowouo ll omen — — team WREN ‘ , COTPUT DATE \TASTATE cour TTT LLL Soe to x ey en Ir or cm} ew CURCNT FIGURE 2: SINGLE ROW BUFFER READ TIMIN
FIGURE 1: AC CHARACTERISTICS -_——, —__ ee ten pl oe cux i tb ow TDR LB /T/L, | twcro—*] ant tence ~ Nowouo ll omen — — team WREN ‘ , COTPUT DATE \TASTATE cour TTT LLL Soe to x ey en Ir or cm} ew CURCNT FIGURE 2: SINGLE ROW BUFFER READ TIMIN
P5 · p05_fig011803×2302px
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) — & °_agzcr< 5 3 “3 c uw gee al ae g FA 3 oI [GH eg 5 F3 oH = Lf 4 Ir} # Z sd 3 e x : je ee E Poo gd Tt 3 5 > 28 a! 3 g a 2 e 5 3 | — 2 g i 8 8 BE RS & a al a 3 £ if 3 OQ) soe Bos 5 2 2 q 2 QO _— Bs aly 3) f 4s 4 £ bE Tin an: 3 2 z 5 wie g By
& °_agzcr< 5 3 “3 c uw gee al ae g FA 3 oI [GH eg 5 F3 oH = Lf 4 Ir} # Z sd 3 e x : je ee E Poo gd Tt 3 5 > 28 a! 3 g a 2 e 5 3 | — 2 g i 8 8 BE RS & a al a 3 £ if 3 OQ) soe Bos 5 2 2 q 2 QO _— Bs aly 3) f 4s 4 £ bE Tin an: 3 2 z 5 wie g By
P6 · p06_fig011803×2302px
CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) — FIGURE 4: TYPICAL READ TIMING FOR SRB CASCADED CONFIGURATION CuK SILI yt nn nn ny yUILN Be as cee ZIT TT 77. Ai MEMORY Ab SRESS —< AD XCEL CAE XRG [CRC Bee es XT TTT YD (CKEN« rr | Vv CURENT, aN Vv outro, —THREESTATE Xa XDT YG SDs XD XD XD
FIGURE 4: TYPICAL READ TIMING FOR SRB CASCADED CONFIGURATION CuK SILI yt nn nn ny yUILN Be as cee ZIT TT 77. Ai MEMORY Ab SRESS —< AD XCEL CAE XRG [CRC Bee es XT TTT YD (CKEN« rr | Vv CURENT, aN Vv outro, —THREESTATE Xa XDT YG SDs XD XD XD

Technical Specifications & Part Details (CRT9006-83HSBIP)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) is a 24-pin standard electronic & interconnect component featuring a 29.94 × 13.70 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
29.94 × 13.70 × 4.20 mm (A1=0.51 mm)
Package family: DIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL)
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol24 auto-grouped pins
OK
IPC-7351B Land Pattern24 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
29.94 × 13.70 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
24P / 24Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL)?

Manufactured by MICROCHIP, the CRT9006-83HSBIP is housed in a PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL package with 24 pins and a 2.54 mm lead pitch. Key pins include: 1 (DOUT3: Multiplexed I/O & Peripheral Pin DOUT3 (General)), 2 (DOUT2: Multiplexed I/O & Peripheral Pin DOUT2 (General)), 3 (DOUT1: Multiplexed I/O & Peripheral Pin DOUT1 (General)), 4 (DOUT0: Multiplexed I/O & Peripheral Pin DOUT0 (General)), 5 (CLK: Multiplexed I/O & Peripheral Pin CLK (General)), 6 (WREN#: Multiplexed I/O & Peripheral Pin WREN# (General)).

What are the IPC-7351B PCB Footprint dimensions for CRT9006-83HSBIP?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CRT9006-83HSBIP (PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) has a nominal body envelope of 13.70 × 29.94 mm, pitch e = 2.54 mm, and 24 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CRT9006-83HSBIP?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CRT9006-83HSBIP (MICROCHIP, PDIP-24_L31.0-W13.5-P2.54-LS15.2-BL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (24 pins) & CRT9006 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DOUT3Digital_IOSignal terminal DOUT3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT3. Supported peripheral buses: General.
2DOUT2Digital_IOSignal terminal DOUT2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT2. Supported peripheral buses: General.
3DOUT1Digital_IOSignal terminal DOUT1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT1. Supported peripheral buses: General.
4DOUT0Digital_IOSignal terminal DOUT0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT0. Supported peripheral buses: General.
5CLKDigital_IOSignal terminal CLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLK. Supported peripheral buses: General.
6WREN#Digital_IOSignal terminal WREN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WREN#. Supported peripheral buses: General.
7CLRCNT#Digital_IOSignal terminal CLRCNT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CLRCNT#. Supported peripheral buses: General.
8CKENDigital_IOSignal terminal CKEN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CKEN. Supported peripheral buses: General.
9DIN0Digital_IOSignal terminal DIN0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN0. Supported peripheral buses: General.
10DIN1Digital_IOSignal terminal DIN1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN1. Supported peripheral buses: General.
11DIN2Digital_IOSignal terminal DIN2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN2. Supported peripheral buses: General.
12DIN3Digital_IOSignal terminal DIN3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN3. Supported peripheral buses: General.
13+5VPower_InPrimary positive power supply input (+5V) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
14DIN4Digital_IOSignal terminal DIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN4. Supported peripheral buses: General.
15DIN5Digital_IOSignal terminal DIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN5. Supported peripheral buses: General.
16DIN6Digital_IOSignal terminal DIN6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN6. Supported peripheral buses: General.
17DIN7Digital_IOSignal terminal DIN7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN7. Supported peripheral buses: General.
18OFDigital_IOSignal terminal OF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OF. Supported peripheral buses: General.
19OE#Digital_IOSignal terminal OE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OE#. Supported peripheral buses: General.
20DOUT7Digital_IOSignal terminal DOUT7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT7. Supported peripheral buses: General.
21DOUT6Digital_IOSignal terminal DOUT6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT6. Supported peripheral buses: General.
22DOUT5Digital_IOSignal terminal DOUT5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT5. Supported peripheral buses: General.
23DOUT4Digital_IOSignal terminal DOUT4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT4. Supported peripheral buses: General.
24GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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