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STM32F446MCY6TR (UFBGA-81) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F446MCY6TR

STID: C2053513UFBGA-81 · 81 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F446MCY6TR (UFBGA-81)A1VDDA2PC12A3PD4A4PD7A5PB3(JTDO/TRAA6PB5A7BOOT0A8VDDA9PE4B1VSSB2PA15(JTDI)B3PD0B4PD6B5PB4(NJTRST)B6PB7B7VSSB8PDR_ONB9VBATC1PA11C2VCAP_2C3PA14(JTCKSWCC4PD1C5PB6C6PB8C7PB9C8PC13C9PC14 - OSC32D1PC9D2PA13(JTMS SWD3PC10D4PC11D5PD2D6PE3D7PE2D8NRSTD9IOD9E1VDDUSBE2PA8E3PA10E4PA12E5PA7J9PA0 WKUP(PA0J8BYPASS_REGJ7PC4J6PB2BOOT1 - (J5PE7J4PE10J3VCAP_1J2VDDJ1PB14H9VDDH8VDDAH7PA4H6PB1H5PE8H4PB10H3VSSH2PB13H1PD11G9PC0G8VSSG7PA1G6PA6G5PE9G4PB12G3PB15G2PD12G1PD13F9PH1 - OSC OUF8PC3F7VSSAF6PA5F5PB0F4PA9F3PC8F2PC7F1PC6E9PH0OSC IN(PHE8PC2E7PA2E6PA3Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.858.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1A2B2C2D2E2F2G2H2J2A3B3C3D3E3F3G3H3J3A4B4C4D4E4F4G4H4J4A5B5C5D5E5F5G5H5J5A6B6C6D6E6F6G6H6J6A7B7C7D7E7F7G7H7J7A8B8C8D8E8F8G8H8J8A9B9C9D9E9F9G9H9J9E=3.70mm · Pitch e=0.40mmD=3.80mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.70mm × 3.80mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (81/81)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A2PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI, I2C)
A3PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART)
A4PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART)
A5PB3(JTDO/TRACES WO)I/OMultiplexed I/O & Peripheral Pin PB3(JTDO/TRACES WO) (SPI, PWM, SWD/JTAG)
A6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, PWM, CAN)
A7BOOT0IInput-Only Pin BOOT0 (General)
A8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A9PE4I/OMultiplexed I/O & Peripheral Pin PE4 (SPI)
B1VSSGNDGround Reference Pin (VSS)
B2PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
B3PD0I/OMultiplexed I/O & Peripheral Pin PD0 (SPI, CAN)
B4PD6I/OMultiplexed I/O & Peripheral Pin PD6 (SPI)
B5PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (SPI, I2C, SWD/JTAG)
B6PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, PWM)
B7VSSGNDGround Reference Pin (VSS)
B8PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
B9VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (PWM, CAN)
C2VCAP_2I/OMultiplexed I/O & Peripheral Pin VCAP_2 (General)
C3PA14(JTCKSWCLK) -I/OMultiplexed I/O & Peripheral Pin PA14(JTCKSWCLK) - (SWD/JTAG)
C4PD1I/OMultiplexed I/O & Peripheral Pin PD1 (SPI, CAN)
C5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C, PWM, CAN)
C6PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C, PWM)
C7PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, PWM)
C8PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
C9PC14 - OSC32 IN(PC14)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(PC14)_ (RTC/CLK)
D1PC9I/OMultiplexed I/O & Peripheral Pin PC9 (PWM, RTC/CLK)
D2PA13(JTMS SWDIO) -I/OMultiplexed I/O & Peripheral Pin PA13(JTMS SWDIO) - (SWD/JTAG)
D3PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
D4PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
D5PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
D6PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
D7PE2I/OMultiplexed I/O & Peripheral Pin PE2 (SPI)
D8NRSTISystem Enable & Hardware Reset (NRST)
D9IOD9I/OGeneral Purpose Digital I/O Pin IOD9
E1VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
E2PA8I/OMultiplexed I/O & Peripheral Pin PA8 (I2C, RTC/CLK)
E3PA10I/OMultiplexed I/O & Peripheral Pin PA10 (PWM)
E4PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
E5PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
E6PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
E7PA2I/OMultiplexed I/O & Peripheral Pin PA2 (SPI, ADC, PWM)
E8PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
E9PH0OSC IN(PH0) -_I/OMultiplexed I/O & Peripheral Pin PH0OSC IN(PH0) -_ (RTC/CLK)
F1PC6I/OMultiplexed I/O & Peripheral Pin PC6 (I2C, PWM)
F2PC7I/OMultiplexed I/O & Peripheral Pin PC7 (UART, SPI, I2C, PWM)
F3PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART, PWM)
F4PA9I/OMultiplexed I/O & Peripheral Pin PA9 (SPI, PWM)
F5PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
F6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
F7VSSAGNDGround Reference Pin (VSSA)
F8PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
F9PH1 - OSC OUT(PH1)_I/OMultiplexed I/O & Peripheral Pin PH1 - OSC OUT(PH1)_ (RTC/CLK)
G1PD13I/OMultiplexed I/O & Peripheral Pin PD13 (SPI, I2C, PWM)
G2PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART, I2C, PWM)
G3PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
G4PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI)
G5PE9I/OMultiplexed I/O & Peripheral Pin PE9 (PWM)
G6PA6I/OMultiplexed I/O & Peripheral Pin PA6 (ADC)
G7PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
G8VSSGNDGround Reference Pin (VSS)
G9PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
H1PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART, I2C)
H2PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
H3VSSGNDGround Reference Pin (VSS)
H4PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, PWM)
H5PE8I/OMultiplexed I/O & Peripheral Pin PE8 (PWM)
H6PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
H7PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
H8VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
J2VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J3VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
J4PE10I/OMultiplexed I/O & Peripheral Pin PE10 (PWM)
J5PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
J6PB2BOOT1 - (PB2)I/OMultiplexed I/O & Peripheral Pin PB2BOOT1 - (PB2) (SPI)
J7PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
J8BYPASS_REGI/OMultiplexed I/O & Peripheral Pin BYPASS_REG (General)
J9PA0 WKUP(PA0) -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP(PA0) - (UART, ADC, PWM)
PIN A1 VDD
Power
Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 26 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F446MCY6TR (ST · UFBGA-81)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F446MCY6TR (UFBGA-81) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F446MCY6TR (UFBGA-81) - 2. Standard Pinout (Top View)
True package pinout (81 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F446MCY6TR (UFBGA-81) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F446MCY6TR (UFBGA-81) - 4. Package Dimensions (D×E×A)
UFBGA-81 · 3.70×3.80mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F446MCY6TR (UFBGA-81) - 5. Recommended Land Pattern
IPC-7351B Footprint (81 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F446MCY6TR (UFBGA-81) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (26 figures · Page 1/3)
Showing 1–12 of 26 uncropped original figures for STM32F446
P1 · p01_fig02EXACT PACKAGE
STM32F446MCY6TR (UFBGA-81) — January 2021 DS10693 Rev 10 1/198
January 2021 DS10693 Rev 10 1/198
P188 · p188_fig01EXACT PACKAGE
STM32F446MCY6TR (UFBGA-81) — Figure 82. WLCSP81 outline
Figure 82. WLCSP81 outline
P1 · p01_fig01881×442px
STM32F446MCY6TR (UFBGA-81) — Arm® Cortex®-M4 32-bit MCU+FPU, 225 DMIPS, up to 512 KB Flash/128+4 KB RAM, USB OTG HS/FS, seventeen TIMs, three ADCs and twenty communication interfaces | Datasheet - production data | LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 x
Arm® Cortex®-M4 32-bit MCU+FPU, 225 DMIPS, up to 512 KB Flash/128+4 KB RAM, USB OTG HS/FS, seventeen TIMs, three ADCs and twenty communication interfaces | Datasheet - production data | LQFP64 (10 × 10 mm) LQFP100 (14 × 14 mm) LQFP144 (20 x
P39 · p39_fig011546×1232px
STM32F446MCY6TR (UFBGA-81) — Figure 10. STM32F446xC/xE LQFP64 pinout
Figure 10. STM32F446xC/xE LQFP64 pinout
P43 · p43_fig011751×1735px
STM32F446MCY6TR (UFBGA-81) — Figure 14. STM32F446xC/xE UFBGA144 ballout
Figure 14. STM32F446xC/xE UFBGA144 ballout
P71 · p71_fig011751×1419px
STM32F446MCY6TR (UFBGA-81) — Figure 18. Power supply scheme VBAT
Figure 18. Power supply scheme VBAT
P143 · p143_fig011546×603px
STM32F446MCY6TR (UFBGA-81) — Figure 46. Typical connection diagram using the ADC
Figure 46. Typical connection diagram using the ADC
P143 · p143_fig021546×1030px
STM32F446MCY6TR (UFBGA-81) — Figure 47. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 47. Power supply and reference decoupling (VREF+ not connected to VDDA)
P183 · p183_fig011548×411px
STM32F446MCY6TR (UFBGA-81) — Figure 77. UFBGA144 recommended footprint
Figure 77. UFBGA144 recommended footprint
P183 · p183_fig021548×1067px
STM32F446MCY6TR (UFBGA-81) — Figure 77. UFBGA144 recommended footprint
Figure 77. UFBGA144 recommended footprint
P186 · p186_fig011548×411px
STM32F446MCY6TR (UFBGA-81) — Figure 80. UFBGA144 recommended footprint
Figure 80. UFBGA144 recommended footprint
P186 · p186_fig021548×1093px
STM32F446MCY6TR (UFBGA-81) — Figure 80. UFBGA144 recommended footprint
Figure 80. UFBGA144 recommended footprint
Page 1 / 3 (26 extracted figures)

Technical Specifications & Part Details (STM32F446MCY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F446MCY6TR (UFBGA-81) is a 81-pin embedded microcontroller unit (mcu) featuring a 3.80 × 3.70 × 0.60 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
180 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
62 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.80 × 3.70 × 0.60 mm (A1=0.17 mm)
Package family: BGA (UFBGA-81)
Pin Count & Lead PitchN / e
81 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2BOOT1 - (PB2)): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol81 auto-grouped pins
OK
IPC-7351B Land Pattern81 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32F446 (16)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (UFBGA-81)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.80 × 3.70 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
81P / 81Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-81
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F446MCY6TR (UFBGA-81)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F446MCY6TR (UFBGA-81)?

Manufactured by ST, the STM32F446MCY6TR is housed in a UFBGA-81 package with 81 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: A1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A2 (PC12: Multiplexed I/O & Peripheral Pin PC12 (UART, SPI, I2C)), A3 (PD4: Multiplexed I/O & Peripheral Pin PD4 (UART)), A4 (PD7: Multiplexed I/O & Peripheral Pin PD7 (UART)), A5 (PB3(JTDO/TRACES WO): Multiplexed I/O & Peripheral Pin PB3(JTDO/TRACES WO) (SPI, PWM, SWD/JTAG)), A6 (PB5: Multiplexed I/O & Peripheral Pin PB5 (SPI, PWM, CAN)).

What are the IPC-7351B PCB Footprint dimensions for STM32F446MCY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F446MCY6TR (UFBGA-81) has a nominal body envelope of 3.70 × 3.80 mm, pitch e = 0.40 mm, and 81 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F446MCY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F446MCY6TR (ST, UFBGA-81) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (81 pins) & STM32F446 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A2PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA, SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C.
A3PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: UART.
A4PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART.
A5PB3(JTDO/TRACES WO)Digital_IOSignal terminal PB3(JTDO/TRACES WO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI3_SCK. Supported peripheral buses: SPI, PWM, SWD/JTAG.
A6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, SPI3_MOSI. Supported peripheral buses: SPI, PWM, CAN.
A7BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A8VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A9PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS. Supported peripheral buses: SPI.
B1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B2PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
B3PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MISO, SPI3_MOSI. Supported peripheral buses: SPI, CAN.
B4PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI.
B5PB4(NJTRST)Digital_IOSignal terminal PB4(NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO, SPI2_NSS. Supported peripheral buses: SPI, I2C, SWD/JTAG.
B6PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, PWM.
B7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B8PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
B9VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: PWM, CAN.
C2VCAP_2Digital_IOSignal terminal VCAP_2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_2. Supported peripheral buses: General.
C3PA14(JTCKSWCLK) -Digital_IOSignal terminal PA14(JTCKSWCLK) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JTCKSWCLK) -. Supported peripheral buses: SWD/JTAG.
C4PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, CAN.
C5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C, PWM, CAN.
C6PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: I2C, PWM.
C7PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, PWM.
C8PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
C9PC14 - OSC32 IN(PC14)_Digital_IOSignal terminal PC14 - OSC32 IN(PC14)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32 IN(PC14)_. Supported peripheral buses: RTC/CLK.
D1PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: PWM, RTC/CLK.
D2PA13(JTMS SWDIO) -Digital_IOSignal terminal PA13(JTMS SWDIO) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMS SWDIO) -. Supported peripheral buses: SWD/JTAG.
D3PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
D4PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISOUSART3RX. Supported peripheral buses: UART, SPI.
D5PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
D6PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
D7PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_SCK. Supported peripheral buses: SPI.
D8NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
D9IOD9Digital_IOGeneral Purpose Digital I/O Pin IOD9
E1VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E2PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: I2C, RTC/CLK.
E3PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: PWM.
E4PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
E5PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
E6PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
E7PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: SPI, ADC, PWM.
E8PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
E9PH0OSC IN(PH0) -_Digital_IOSignal terminal PH0OSC IN(PH0) -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN(PH0) -_. Supported peripheral buses: RTC/CLK.
F1PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: I2C, PWM.
F2PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM.
F3PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART, PWM.
F4PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI, PWM.
F5PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI, ADC, PWM.
F6PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM.
F7VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
F8PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
F9PH1 - OSC OUT(PH1)_Digital_IOSignal terminal PH1 - OSC OUT(PH1)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC OUT(PH1)_. Supported peripheral buses: RTC/CLK.
G1PD13Digital_IOSignal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: SPI, I2C, PWM.
G2PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: UART, I2C, PWM.
G3PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM, RTC/CLK.
G4PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI.
G5PE9Digital_IOSignal terminal PE9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: PWM.
G6PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: ADC.
G7PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
G8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
G9PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
H1PD11Digital_IOSignal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: UART, I2C.
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