ChipDocs.org
⌘K
2284 PARTSUpload PDF
STM32F446RET6 (LQFP-64(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F446RET6

STID: C69336LQFP-64(10x10) · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F446RET6 (LQFP-64(10x10))1VBAT2PC133PC14 - OSC324NC5PH0OSC IN(PH6PH1 - OSC OU7NRST8PC09PC110PC211PC312VSSA13VDDA14PA0 WKUP(PA015PA116PA217PA318VSS19VDD20PA421PA522PA623PA724PC425PC526PB027PB128PB2BOOT1 - (29PB1030VCAP_131VSS32VDD64VDD63VSS62PB961PB860BOOT059PB758PB657PB556PB4(NJTRST)55PB3(JTDO/TRA54PD253PC1252PC1151PC1050PA15(JTDI)49PA14(JTCKSWC48VDD47VSS46PA13(JTMSSWD45PA1244PA1143PA1042PA941PA840PC939PC838PC737PC636PB1535PB1434PB1333PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
3PC14 - OSC32 IN(PC14)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(PC14)_ (RTC/CLK)
4NCNCNo Connect (Leave Floating)
5PH0OSC IN(PH0) -_I/OMultiplexed I/O & Peripheral Pin PH0OSC IN(PH0) -_ (RTC/CLK)
6PH1 - OSC OUT(PH1)_I/OMultiplexed I/O & Peripheral Pin PH1 - OSC OUT(PH1)_ (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
9PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC)
10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
11PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
12VSSAGNDGround Reference Pin (VSSA)
13VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
14PA0 WKUP(PA0) -I/OMultiplexed I/O & Peripheral Pin PA0 WKUP(PA0) - (UART, ADC, PWM)
15PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC, PWM)
16PA2I/OMultiplexed I/O & Peripheral Pin PA2 (SPI, ADC, PWM)
17PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
18VSSGNDGround Reference Pin (VSS)
19VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
20PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
21PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
22PA6I/OMultiplexed I/O & Peripheral Pin PA6 (ADC)
23PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
24PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
25PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
26PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
27PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
28PB2BOOT1 - (PB2)I/OMultiplexed I/O & Peripheral Pin PB2BOOT1 - (PB2) (SPI)
29PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, PWM)
30VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
31VSSGNDGround Reference Pin (VSS)
32VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
33PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI)
34PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
35PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
36PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
37PC6I/OMultiplexed I/O & Peripheral Pin PC6 (I2C, PWM)
38PC7I/OMultiplexed I/O & Peripheral Pin PC7 (UART, SPI, I2C, PWM)
39PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART, PWM)
40PC9I/OMultiplexed I/O & Peripheral Pin PC9 (PWM, RTC/CLK)
41PA8I/OMultiplexed I/O & Peripheral Pin PA8 (I2C, RTC/CLK)
42PA9I/OMultiplexed I/O & Peripheral Pin PA9 (SPI, PWM)
43PA10I/OMultiplexed I/O & Peripheral Pin PA10 (PWM)
44PA11I/OMultiplexed I/O & Peripheral Pin PA11 (PWM, CAN)
45PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
46PA13(JTMSSWDIO) -I/OMultiplexed I/O & Peripheral Pin PA13(JTMSSWDIO) - (SWD/JTAG)
47VSSGNDGround Reference Pin (VSS)
48VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
49PA14(JTCKSWCLK) -I/OMultiplexed I/O & Peripheral Pin PA14(JTCKSWCLK) - (SWD/JTAG)
50PA15(JTDI)I/OMultiplexed I/O & Peripheral Pin PA15(JTDI) (UART, SPI, SWD/JTAG)
51PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
52PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
53PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI, I2C)
54PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
55PB3(JTDO/TRACES WO)I/OMultiplexed I/O & Peripheral Pin PB3(JTDO/TRACES WO) (SPI, PWM, SWD/JTAG)
56PB4(NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4(NJTRST) (SPI, I2C, SWD/JTAG)
57PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, PWM, CAN)
58PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C, PWM, CAN)
59PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, PWM)
60BOOT0IInput-Only Pin BOOT0 (General)
61PB8I/OMultiplexed I/O & Peripheral Pin PB8 (I2C, PWM)
62PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, PWM)
63VSSGNDGround Reference Pin (VSS)
64VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F446RET6 (ST · LQFP-64(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F446RET6 (LQFP-64(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F446RET6 (LQFP-64(10x10)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F446RET6 (LQFP-64(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F446RET6 (LQFP-64(10x10)) - 4. Package Dimensions (D×E×A)
LQFP-64(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F446RET6 (LQFP-64(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F446RET6 (LQFP-64(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32F446
P1 · p01_fig01EXACT PACKAGE
STM32F446RET6 (LQFP-64(10x10)) — ARM® Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 512kB Flash/128+4KB RAM, | USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces | Datasheet - production data | LQFP64 (10 × 10mm) LQFP100 (14 × 14mm) LQFP144 (20 x 20 mm) | UFBGA144 (7 x 7 mm) |
ARM® Cortex®-M4 32b MCU+FPU, 225DMIPS, up to 512kB Flash/128+4KB RAM, | USB OTG HS/FS, 17 TIMs, 3 ADCs, 20 comm. interfaces | Datasheet - production data | LQFP64 (10 × 10mm) LQFP100 (14 × 14mm) LQFP144 (20 x 20 mm) | UFBGA144 (7 x 7 mm) |
P1 · p01_fig02EXACT PACKAGE
STM32F446RET6 (LQFP-64(10x10)) — September 2016 DocID027107 Rev 6 1/202
September 2016 DocID027107 Rev 6 1/202
P41 · p41_fig01EXACT PACKAGE
STM32F446RET6 (LQFP-64(10x10)) — Figure 10. STM32F446xC/xE LQFP64 pinout
Figure 10. STM32F446xC/xE LQFP64 pinout
P176 · p176_fig01EXACT PACKAGE
STM32F446RET6 (LQFP-64(10x10)) — Figure 67. LQFP64-10x10 mm 64 pin low-profile quad flat package outline 6($7,1*3/$1( &
Figure 67. LQFP64-10x10 mm 64 pin low-profile quad flat package outline 6($7,1*3/$1( &
P177 · p177_fig01EXACT PACKAGE
STM32F446RET6 (LQFP-64(10x10)) — Figure 68. LQFP64 Recommended footprint
Figure 68. LQFP64 Recommended footprint
P41 · p41_fig01P41
STM32F446RET6 (LQFP-64(10x10)) — Datasheet Page 41 (p41_fig01)
Datasheet Page 41 (p41_fig01)
P73 · p73_fig011751×1451px
STM32F446RET6 (LQFP-64(10x10)) — Figure 18. Power supply scheme
Figure 18. Power supply scheme
P73 · p73_fig01P73
STM32F446RET6 (LQFP-64(10x10)) — Datasheet Page 73 (p73_fig01)
Datasheet Page 73 (p73_fig01)
P77 · p77_fig011875×2535px
STM32F446RET6 (LQFP-64(10x10)) — STM32F446xC/E Electrical characteristics
STM32F446xC/E Electrical characteristics
P176 · p176_fig01P176
STM32F446RET6 (LQFP-64(10x10)) — Datasheet Page 176 (p176_fig01)
Datasheet Page 176 (p176_fig01)
P177 · p177_fig01P177
STM32F446RET6 (LQFP-64(10x10)) — Datasheet Page 177 (p177_fig01)
Datasheet Page 177 (p177_fig01)
P193 · p193_fig011548×804px
STM32F446RET6 (LQFP-64(10x10)) — Figure 83. WLCSP81- 81-pin, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
Figure 83. WLCSP81- 81-pin, 4.4084 x 3.7594 mm, 0.4 mm pitch wafer level chip scale
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32F446RET6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F446RET6 (LQFP-64(10x10)) is a 64-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
180 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
48 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, CAN, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2BOOT1 - (PB2), BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-64(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F446RET6 (LQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F446RET6 (LQFP-64(10x10))?

Manufactured by ST, the STM32F446RET6 is housed in a LQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), 3 (PC14 - OSC32 IN(PC14)_: Multiplexed I/O & Peripheral Pin PC14 - OSC32 IN(PC14)_ (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0OSC IN(PH0) -_: Multiplexed I/O & Peripheral Pin PH0OSC IN(PH0) -_ (RTC/CLK)), 6 (PH1 - OSC OUT(PH1)_: Multiplexed I/O & Peripheral Pin PH1 - OSC OUT(PH1)_ (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32F446RET6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F446RET6 (LQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F446RET6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F446RET6 (ST, LQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32F446 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
3PC14 - OSC32 IN(PC14)_Digital_IOSignal terminal PC14 - OSC32 IN(PC14)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32 IN(PC14)_. Supported peripheral buses: RTC/CLK.
4NCNo_ConnectNo Connect (Leave Floating)
5PH0OSC IN(PH0) -_Digital_IOSignal terminal PH0OSC IN(PH0) -_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0OSC IN(PH0) -_. Supported peripheral buses: RTC/CLK.
6PH1 - OSC OUT(PH1)_Digital_IOSignal terminal PH1 - OSC OUT(PH1)_ (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC OUT(PH1)_. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
9PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI, SPI2_MOSI. Supported peripheral buses: SPI, I2C, ADC.
10PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
11PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
12VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
14PA0 WKUP(PA0) -Digital_IOSignal terminal PA0 WKUP(PA0) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0 WKUP(PA0) -. Supported peripheral buses: UART, ADC, PWM.
15PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM.
16PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: SPI, ADC, PWM.
17PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
18VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
19VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
20PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
21PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM.
22PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA6. Supported peripheral buses: ADC.
23PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC, PWM.
24PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
25PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: UART, ADC.
26PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI, ADC, PWM.
27PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
28PB2BOOT1 - (PB2)Digital_IOSignal terminal PB2BOOT1 - (PB2) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: SPI.
29PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
30VCAP_1Digital_IOSignal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
31VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
32VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: UART, SPI.
34PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
35PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM.
36PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, PWM, RTC/CLK.
37PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: I2C, PWM.
38PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM.
39PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART, PWM.
40PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: PWM, RTC/CLK.
41PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: I2C, RTC/CLK.
42PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI, PWM.
43PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: PWM.
44PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: PWM, CAN.
45PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
46PA13(JTMSSWDIO) -Digital_IOSignal terminal PA13(JTMSSWDIO) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13(JTMSSWDIO) -. Supported peripheral buses: SWD/JTAG.
47VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
48VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
49PA14(JTCKSWCLK) -Digital_IOSignal terminal PA14(JTCKSWCLK) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14(JTCKSWCLK) -. Supported peripheral buses: SWD/JTAG.
50PA15(JTDI)Digital_IOSignal terminal PA15(JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSS, SPI3_NSS. Supported peripheral buses: UART, SPI, SWD/JTAG.
51PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
52PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISOUSART3RX. Supported peripheral buses: UART, SPI.
53PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA, SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C.
54PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
55PB3(JTDO/TRACES WO)Digital_IOSignal terminal PB3(JTDO/TRACES WO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SCK, SPI3_SCK. Supported peripheral buses: SPI, PWM, SWD/JTAG.
56PB4(NJTRST)Digital_IOSignal terminal PB4(NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO, SPI2_NSS. Supported peripheral buses: SPI, I2C, SWD/JTAG.
57PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI, SPI3_MOSI. Supported peripheral buses: SPI, PWM, CAN.
58PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: I2C, PWM, CAN.
59PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, PWM.
60BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
61PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: I2C, PWM.
62PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI, PWM.
63VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
64VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
ExplorePartsPackagesMFRsUpload