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- · 40P
Synchronized Pinout (Symbol / 2D / 3D) (40/40)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VA2 | I/O | Multiplexed I/O & Peripheral Pin VA2 (General) |
| 2 | VA10 | I/O | Multiplexed I/O & Peripheral Pin VA10 (General) |
| 3 | VA3 | I/O | Multiplexed I/O & Peripheral Pin VA3 (General) |
| 4 | VA11 | I/O | Multiplexed I/O & Peripheral Pin VA11 (General) |
| 5 | VA12 | I/O | Multiplexed I/O & Peripheral Pin VA12 (General) |
| 6 | VA4 | I/O | Multiplexed I/O & Peripheral Pin VA4 (General) |
| 7 | VA13 | I/O | Multiplexed I/O & Peripheral Pin VA13 (General) |
| 8 | VA5 | I/O | Multiplexed I/O & Peripheral Pin VA5 (General) |
| 9 | VA6 | I/O | Multiplexed I/O & Peripheral Pin VA6 (General) |
| 10 | VA7 | I/O | Multiplexed I/O & Peripheral Pin VA7 (General) |
| 11 | VLT | I/O | Multiplexed I/O & Peripheral Pin VLT (General) |
| 12 | VS# | I/O | Multiplexed I/O & Peripheral Pin VS# (General) |
| 13 | HS# | I/O | Multiplexed I/O & Peripheral Pin HS# (General) |
| 14 | CCLK# | I/O | Multiplexed I/O & Peripheral Pin CCLK# (General) |
| 15 | DRB# | I/O | Multiplexed I/O & Peripheral Pin DRB# (General) |
| 16 | VD7 | I/O | Multiplexed I/O & Peripheral Pin VD7 (General) |
| 17 | VD6 | I/O | Multiplexed I/O & Peripheral Pin VD6 (General) |
| 18 | VD5 | I/O | Multiplexed I/O & Peripheral Pin VD5 (General) |
| 19 | VD4 | I/O | Multiplexed I/O & Peripheral Pin VD4 (General) |
| 20 | VD3 | I/O | Multiplexed I/O & Peripheral Pin VD3 (General) |
| 21 | +5V | Power | Power Supply Input (+5V — 3.3V / 5.0V Standard Logic) |
| 22 | VD2 | I/O | Multiplexed I/O & Peripheral Pin VD2 (General) |
| 23 | VD1 | I/O | Multiplexed I/O & Peripheral Pin VD1 (General) |
| 24 | VD0 | I/O | Multiplexed I/O & Peripheral Pin VD0 (General) |
| 25 | CS# | I/O | Multiplexed I/O & Peripheral Pin CS# (General) |
| 26 | RST# | I/O | Multiplexed I/O & Peripheral Pin RST# (General) |
| 27 | INT | I/O | Multiplexed I/O & Peripheral Pin INT (General) |
| 28 | DMAR/SL3/VBLANK | I/O | Multiplexed I/O & Peripheral Pin DMAR/SL3/VBLANK (General) |
| 29 | WBEN/SL2/CSYNC# | I/O | Multiplexed I/O & Peripheral Pin WBEN/SL2/CSYNC# (General) |
| 30 | SLG#/SL1 | I/O | Multiplexed I/O & Peripheral Pin SLG#/SL1 (General) |
| 31 | SLD/SL0 | I/O | Multiplexed I/O & Peripheral Pin SLD/SL0 (General) |
| 32 | CSYNC#/LPSTB | I/O | Multiplexed I/O & Peripheral Pin CSYNC#/LPSTB (General) |
| 33 | ACK/TSC# | I/O | Multiplexed I/O & Peripheral Pin ACK/TSC# (General) |
| 34 | CURS | I/O | Multiplexed I/O & Peripheral Pin CURS (General) |
| 35 | CBLANK | I/O | Multiplexed I/O & Peripheral Pin CBLANK (General) |
| 36 | VA0 | I/O | Multiplexed I/O & Peripheral Pin VA0 (General) |
| 37 | VA8 | I/O | Multiplexed I/O & Peripheral Pin VA8 (General) |
| 38 | VA1 | I/O | Multiplexed I/O & Peripheral Pin VA1 (General) |
| 39 | VA9 | I/O | Multiplexed I/O & Peripheral Pin VA9 (General) |
| 40 | GND | GND | Ground Reference Pin (GND) |
PIN 1 VA2
I/OMultiplexed I/O & Peripheral Pin VA2 (General)
Design note: Signal terminal VA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (40 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL · 13.90×50.26mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (40 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for CRT9007
P1 · p01_fig011803×2302px
P1 · p01_fig01P1
P2 · p02_fig011803×2302px
P20 · p20_fig011803×2302px
P21 · p21_fig011803×2302px
P22 · p22_fig011803×2302px
Technical Specifications & Part Details (CRT9007BNP)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CRT9007BNP (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) is a 40-pin standard electronic & interconnect component featuring a 50.26 × 13.90 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
50.26 × 13.90 × 4.20 mm (A1=0.51 mm)
Package family: DIP (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol40 auto-grouped pins
IPC-7351B Land Pattern40 pads · Pitch 2.54mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CRT9007 (2)
- · 40P
Mechanical Dimensions & Land Pattern (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
50.26 × 13.90 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
40P / 40Pad (THT_DIP)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CRT9007BNP (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CRT9007BNP (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL)?
Manufactured by MICROCHIP, the CRT9007BNP is housed in a PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL package with 40 pins and a 2.54 mm lead pitch. Key pins include: 1 (VA2: Multiplexed I/O & Peripheral Pin VA2 (General)), 2 (VA10: Multiplexed I/O & Peripheral Pin VA10 (General)), 3 (VA3: Multiplexed I/O & Peripheral Pin VA3 (General)), 4 (VA11: Multiplexed I/O & Peripheral Pin VA11 (General)), 5 (VA12: Multiplexed I/O & Peripheral Pin VA12 (General)), 6 (VA4: Multiplexed I/O & Peripheral Pin VA4 (General)).
What are the IPC-7351B PCB Footprint dimensions for CRT9007BNP?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CRT9007BNP (PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) has a nominal body envelope of 13.90 × 50.26 mm, pitch e = 2.54 mm, and 40 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CRT9007BNP?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CRT9007BNP (MICROCHIP, PDIP-40_L51.8-W13.5-P2.54-LS15.4-BL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (40 pins) & CRT9007 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VA2 | Digital_IO | Signal terminal VA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA2. Supported peripheral buses: General. |
| 2 | VA10 | Digital_IO | Signal terminal VA10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA10. Supported peripheral buses: General. |
| 3 | VA3 | Digital_IO | Signal terminal VA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA3. Supported peripheral buses: General. |
| 4 | VA11 | Digital_IO | Signal terminal VA11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA11. Supported peripheral buses: General. |
| 5 | VA12 | Digital_IO | Signal terminal VA12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA12. Supported peripheral buses: General. |
| 6 | VA4 | Digital_IO | Signal terminal VA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA4. Supported peripheral buses: General. |
| 7 | VA13 | Digital_IO | Signal terminal VA13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA13. Supported peripheral buses: General. |
| 8 | VA5 | Digital_IO | Signal terminal VA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA5. Supported peripheral buses: General. |
| 9 | VA6 | Digital_IO | Signal terminal VA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA6. Supported peripheral buses: General. |
| 10 | VA7 | Digital_IO | Signal terminal VA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA7. Supported peripheral buses: General. |
| 11 | VLT | Digital_IO | Signal terminal VLT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VLT. Supported peripheral buses: General. |
| 12 | VS# | Digital_IO | Signal terminal VS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VS#. Supported peripheral buses: General. |
| 13 | HS# | Digital_IO | Signal terminal HS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HS#. Supported peripheral buses: General. |
| 14 | CCLK# | Digital_IO | Signal terminal CCLK# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CCLK#. Supported peripheral buses: General. |
| 15 | DRB# | Digital_IO | Signal terminal DRB# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DRB#. Supported peripheral buses: General. |
| 16 | VD7 | Digital_IO | Signal terminal VD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD7. Supported peripheral buses: General. |
| 17 | VD6 | Digital_IO | Signal terminal VD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD6. Supported peripheral buses: General. |
| 18 | VD5 | Digital_IO | Signal terminal VD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD5. Supported peripheral buses: General. |
| 19 | VD4 | Digital_IO | Signal terminal VD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD4. Supported peripheral buses: General. |
| 20 | VD3 | Digital_IO | Signal terminal VD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD3. Supported peripheral buses: General. |
| 21 | +5V | Power_In | Primary positive power supply input (+5V) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 22 | VD2 | Digital_IO | Signal terminal VD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD2. Supported peripheral buses: General. |
| 23 | VD1 | Digital_IO | Signal terminal VD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD1. Supported peripheral buses: General. |
| 24 | VD0 | Digital_IO | Signal terminal VD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VD0. Supported peripheral buses: General. |
| 25 | CS# | Digital_IO | Signal terminal CS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General. |
| 26 | RST# | Digital_IO | Signal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General. |
| 27 | INT | Digital_IO | Signal terminal INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT. Supported peripheral buses: General. |
| 28 | DMAR/SL3/VBLANK | Digital_IO | Signal terminal DMAR/SL3/VBLANK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DMAR/SL3/VBLANK. Supported peripheral buses: General. |
| 29 | WBEN/SL2/CSYNC# | Digital_IO | Signal terminal WBEN/SL2/CSYNC# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WBEN/SL2/CSYNC#. Supported peripheral buses: General. |
| 30 | SLG#/SL1 | Digital_IO | Signal terminal SLG#/SL1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLG#/SL1. Supported peripheral buses: General. |
| 31 | SLD/SL0 | Digital_IO | Signal terminal SLD/SL0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SLD/SL0. Supported peripheral buses: General. |
| 32 | CSYNC#/LPSTB | Digital_IO | Signal terminal CSYNC#/LPSTB (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CSYNC#/LPSTB. Supported peripheral buses: General. |
| 33 | ACK/TSC# | Digital_IO | Signal terminal ACK/TSC# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ACK/TSC#. Supported peripheral buses: General. |
| 34 | CURS | Digital_IO | Signal terminal CURS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CURS. Supported peripheral buses: General. |
| 35 | CBLANK | Digital_IO | Signal terminal CBLANK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CBLANK. Supported peripheral buses: General. |
| 36 | VA0 | Digital_IO | Signal terminal VA0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA0. Supported peripheral buses: General. |
| 37 | VA8 | Digital_IO | Signal terminal VA8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA8. Supported peripheral buses: General. |
| 38 | VA1 | Digital_IO | Signal terminal VA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA1. Supported peripheral buses: General. |
| 39 | VA9 | Digital_IO | Signal terminal VA9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: VA9. Supported peripheral buses: General. |
| 40 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |