![CH372B (SSOP-20) — CH372 内置了USB 通讯中的底层协议，具有省事的内置固件模式和灵活的外置固件模式。在内置 固件模式下，CH372 自动处理默认端点0 的所有事务，本地端单片机只要负责数据交换，所以单片机 程序非常简洁。在外置固件模式下，由外部单片机根据需要自行处理各种USB 请求，从而可以实现符 合各种USB 类规范的设备。 | 2、特点 | CS# | INT# | D- | D+ | WR# RD# A0 | D [7-0] | CH372 接口芯片 | 本地端 控制器 | 单片机](/api/v1/assets/C20416856/extracted/figures/p01_fig01.png)
SSOP-20 · 20P
Synchronized Pinout (Symbol / 2D / 3D) (20/20)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | INT# | I/O | Multiplexed I/O & Peripheral Pin INT# (General) |
| 2 | WR# | I/O | Multiplexed I/O & Peripheral Pin WR# (General) |
| 3 | RD# | I/O | Multiplexed I/O & Peripheral Pin RD# (General) |
| 4 | A0 | I/O | Multiplexed I/O & Peripheral Pin A0 (General) |
| 5 | V3 | Power | Regulated Power Output (V3 — 3.3V to 5V) |
| 6 | UD+ | I/O | Multiplexed I/O & Peripheral Pin UD+ (USB) |
| 7 | UD- | I/O | Multiplexed I/O & Peripheral Pin UD- (USB) |
| 8 | XI | I/O | XI (RTC/CLK) |
| 9 | XO | I/O | XO (RTC/CLK) |
| 10 | D0 | I/O | Multiplexed I/O & Peripheral Pin D0 (General) |
| 11 | D1 | I/O | Multiplexed I/O & Peripheral Pin D1 (General) |
| 12 | D2 | I/O | Multiplexed I/O & Peripheral Pin D2 (General) |
| 13 | D3 | I/O | Multiplexed I/O & Peripheral Pin D3 (General) |
| 14 | D4 | I/O | Multiplexed I/O & Peripheral Pin D4 (General) |
| 15 | D5 | I/O | Multiplexed I/O & Peripheral Pin D5 (General) |
| 16 | D6 | I/O | Multiplexed I/O & Peripheral Pin D6 (General) |
| 17 | D7 | I/O | Multiplexed I/O & Peripheral Pin D7 (General) |
| 18 | GND | GND | Ground Reference Pin (GND) |
| 19 | CS# | I/O | Multiplexed I/O & Peripheral Pin CS# (General) |
| 20 | VCC | Power | Power Supply Input (VCC — 3.3V to 5V) |
PIN 1 INT#
I/OMultiplexed I/O & Peripheral Pin INT# (General)
Design note: 中断请求输出 低电平有效 ，
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SSOP-20 · 5.30×7.20mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH372
P1 · p01_fig011680×1014px
P2 · p02_fig01434×434px
P2 · p02_fig01P2
P12 · p12_fig011236×581px
P12 · p12_fig02998×510px
P13 · p13_fig011111×705px
P13 · p13_fig021448×581px
P13 · p13_fig01P13
Technical Specifications & Part Details (CH372B)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH372B (SSOP-20) is a 20-pin standard electronic & interconnect component featuring a 7.20 × 5.30 × 1.85 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.20 × 5.30 × 1.85 mm (A1=0.15 mm)
Package family: TSSOP (SSOP-20)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol20 auto-grouped pins
IPC-7351B Land Pattern20 pads · Pitch 0.65mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH372 (3)
Mechanical Dimensions & Land Pattern (SSOP-20)
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.20 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=1.85mm · e=0.65mm
Pad Size (W × L)Level B
0.42 × 1.60 mm
Pins / Total PadsTopology
20P / 20Pad (DUAL_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit SSOP-20 | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH372B (SSOP-20)
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH372B (SSOP-20)?
Manufactured by WCH, the CH372B is housed in a SSOP-20 package with 20 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (INT#: Multiplexed I/O & Peripheral Pin INT# (General)), 2 (WR#: Multiplexed I/O & Peripheral Pin WR# (General)), 3 (RD#: Multiplexed I/O & Peripheral Pin RD# (General)), 4 (A0: Multiplexed I/O & Peripheral Pin A0 (General)), 5 (V3: Regulated Power Output (V3 — 3.3V to 5V)), 6 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)).
What are the IPC-7351B PCB Footprint dimensions for CH372B?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH372B (SSOP-20) has a nominal body envelope of 5.30 × 7.20 mm, pitch e = 0.65 mm, and 20 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH372B?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH372B (WCH, SSOP-20) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (20 pins) & CH372 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | INT# | Digital_IO | Signal terminal INT# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General. |
| 2 | WR# | Digital_IO | Signal terminal WR# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: WR#. Supported peripheral buses: General. |
| 3 | RD# | Digital_IO | Signal terminal RD# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: RD#. Supported peripheral buses: General. |
| 4 | A0 | Digital_IO | Signal terminal A0 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: A0. Supported peripheral buses: General. |
| 5 | V3 | Power_Out | Regulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V). |
| 6 | UD+ | Digital_IO | Signal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB. |
| 7 | UD- | Digital_IO | Signal terminal UD- (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB. |
| 8 | XI | Digital_IO | 12 MHz crystal oscillator input (XI); requires a 22pF load capacitor to GND (internally clocked on CH340C). |
| 9 | XO | Digital_IO | 12 MHz crystal oscillator inverted output (XO); connect to crystal terminal and 22pF load capacitor to GND. |
| 10 | D0 | Digital_IO | Signal terminal D0 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D0. Supported peripheral buses: General. |
| 11 | D1 | Digital_IO | Signal terminal D1 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D1. Supported peripheral buses: General. |
| 12 | D2 | Digital_IO | Signal terminal D2 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D2. Supported peripheral buses: General. |
| 13 | D3 | Digital_IO | Signal terminal D3 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D3. Supported peripheral buses: General. |
| 14 | D4 | Digital_IO | Signal terminal D4 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D4. Supported peripheral buses: General. |
| 15 | D5 | Digital_IO | Signal terminal D5 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D5. Supported peripheral buses: General. |
| 16 | D6 | Digital_IO | Signal terminal D6 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D6. Supported peripheral buses: General. |
| 17 | D7 | Digital_IO | Signal terminal D7 (I/O, 3.3V to 5V domain). Multiplexed alternate functions: D7. Supported peripheral buses: General. |
| 18 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 19 | CS# | Digital_IO | Signal terminal CS# (I/O, 3.3V to 5V domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General. |
| 20 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 3.3V to 5V domain (Max rating: 5.0V). |