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C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) — Symbol, Footprint IPC-7351B & 3D STEP Model

C19397197

SemiconductorUFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6 · 49 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6)1VDD_24MHZ2VDD_VCO3RF_P4RF_N5VDD_RF6RF_TX_ALT_P7RF_TX_ALT_N8VDD_IF9BIAS_R10VDD_PADSA11PC5/TX_ACTIV12nRESET13IO1514IO1615VREG_OUT16VDD_PADS17VDD_CORE18PA7/TIM1_CH419IO2020IO921PA0/TIM2_CH122IO1123VDD_PADS24IO1325IO1449GND48OSC_OUT47OSC_IN46VDD_SYNTH45VDD_PRE44VDD_CORE43IO4342PB6/ADC1/IRQ41PB7/ADC2/IRQ40IO4039VDD_MEM38IO3837VDD_PADS36IO3635PC4/JTMS/SWD34PC3/JTDI33PC2/JTDO/SWO32SWCLK/JTCK31IO3130IO3029PA6/TIM1_CH328VDD_PADS27IO4726IO21Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849E=7.00mm · Pitch e=0.50mmD=7.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (49/49)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VDD_24MHZPowerPower Supply Input (VDD_24MHZ — 3.3V / 5.0V Standard Logic)
2VDD_VCOPowerPower Supply Input (VDD_VCO — 3.3V / 5.0V Standard Logic)
3RF_PI/OMultiplexed I/O & Peripheral Pin RF_P (General)
4RF_NI/OMultiplexed I/O & Peripheral Pin RF_N (General)
5VDD_RFPowerPower Supply Input (VDD_RF — 3.3V / 5.0V Standard Logic)
6RF_TX_ALT_PI/OMultiplexed I/O & Peripheral Pin RF_TX_ALT_P (General)
7RF_TX_ALT_NI/OMultiplexed I/O & Peripheral Pin RF_TX_ALT_N (General)
8VDD_IFPowerPower Supply Input (VDD_IF — 3.3V / 5.0V Standard Logic)
9BIAS_RI/OMultiplexed I/O & Peripheral Pin BIAS_R (General)
10VDD_PADSAPowerPower Supply Input (VDD_PADSA — 3.3V / 5.0V Standard Logic)
11PC5/TX_ACTIVEI/OMultiplexed I/O & Peripheral Pin PC5/TX_ACTIVE (General)
12nRESETISystem Enable & Hardware Reset (nRESET)
13IO15I/OGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16I/OGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15VREG_OUTPowerPower Supply Input (VREG_OUT — 3.3V / 5.0V Standard Logic)
16VDD_PADSPowerPower Supply Input (VDD_PADS — 3.3V / 5.0V Standard Logic)
17VDD_COREPowerPower Supply Input (VDD_CORE — 3.3V / 5.0V Standard Logic)
18PA7/TIM1_CH4/REG_ENI/OMultiplexed I/O & Peripheral Pin PA7/TIM1_CH4/REG_EN (PWM)
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9I/OGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21PA0/TIM2_CH1/SC2MOSII/OMultiplexed I/O & Peripheral Pin PA0/TIM2_CH1/SC2MOSI (PWM)
22IO11I/OGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23VDD_PADSPowerPower Supply Input (VDD_PADS — 3.3V / 5.0V Standard Logic)
24IO13I/OGPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25IO14I/OGPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26IO21I/OGPIO21 / RTC_GPIO21
27IO47I/OGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28VDD_PADSPowerPower Supply Input (VDD_PADS — 3.3V / 5.0V Standard Logic)
29PA6/TIM1_CH3I/OMultiplexed I/O & Peripheral Pin PA6/TIM1_CH3 (PWM)
30IO30I/OGeneral Purpose Digital I/O Pin IO30
31IO31I/OGeneral Purpose Digital I/O Pin IO31
32SWCLK/JTCKI/OMultiplexed I/O & Peripheral Pin SWCLK/JTCK (SWD/JTAG)
33PC2/JTDO/SWOI/OMultiplexed I/O & Peripheral Pin PC2/JTDO/SWO (SWD/JTAG)
34PC3/JTDII/OMultiplexed I/O & Peripheral Pin PC3/JTDI (SWD/JTAG)
35PC4/JTMS/SWDIOI/OMultiplexed I/O & Peripheral Pin PC4/JTMS/SWDIO (SWD/JTAG)
36IO36I/OGeneral Purpose Digital I/O Pin IO36
37VDD_PADSPowerPower Supply Input (VDD_PADS — 3.3V / 5.0V Standard Logic)
38IO38I/OGeneral Purpose Digital I/O Pin IO38
39VDD_MEMPowerPower Supply Input (VDD_MEM — 3.3V / 5.0V Standard Logic)
40IO40I/OGeneral Purpose Digital I/O Pin IO40
41PB7/ADC2/IRQC/TIM1_CH2I/OMultiplexed I/O & Peripheral Pin PB7/ADC2/IRQC/TIM1_CH2 (ADC, PWM)
42PB6/ADC1/IRQB/TIM1_CH1I/OMultiplexed I/O & Peripheral Pin PB6/ADC1/IRQB/TIM1_CH1 (ADC, PWM)
43IO43I/OGeneral Purpose Digital I/O Pin IO43
44VDD_COREPowerPower Supply Input (VDD_CORE — 3.3V / 5.0V Standard Logic)
45VDD_PREPowerPower Supply Input (VDD_PRE — 3.3V / 5.0V Standard Logic)
46VDD_SYNTHPowerPower Supply Input (VDD_SYNTH — 3.3V / 5.0V Standard Logic)
47OSC_INI/OMultiplexed I/O & Peripheral Pin OSC_IN (RTC/CLK)
48OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
49GNDGNDExposed Thermal & Ground Pad (GND)
PIN 1 VDD_24MHZ
Power
Power Supply Input (VDD_24MHZ — 3.3V / 5.0V Standard Logic)
Design note: Primary positive power supply input (VDD_24MHZ) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C19397197 (Semiconductor · UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) - 2. Standard Pinout (Top View)
True package pinout (49 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) - 4. Package Dimensions (D×E×A)
UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) - 5. Recommended Land Pattern
IPC-7351B Footprint (49 Pads)Expand ›
6. Application SchematicSCHEMATIC
C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C19397197)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 0.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated ADC, PWM, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.60 mm (A1=0.03 mm)
Package family: QFN (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6)
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
ADC, PWM, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol49 auto-grouped pins
OK
IPC-7351B Land Pattern49 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 5.60×5.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.60mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.85 mm
Pins / Total PadsTopology
49P / 49Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6)?

Manufactured by Semiconductor, the C19397197 is housed in a UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6 package with 49 pins and a 0.50 mm lead pitch. Key pins include: 1 (VDD_24MHZ: Power Supply Input (VDD_24MHZ — 3.3V / 5.0V Standard Logic)), 2 (VDD_VCO: Power Supply Input (VDD_VCO — 3.3V / 5.0V Standard Logic)), 3 (RF_P: Multiplexed I/O & Peripheral Pin RF_P (General)), 4 (RF_N: Multiplexed I/O & Peripheral Pin RF_N (General)), 5 (VDD_RF: Power Supply Input (VDD_RF — 3.3V / 5.0V Standard Logic)), 6 (RF_TX_ALT_P: Multiplexed I/O & Peripheral Pin RF_TX_ALT_P (General)).

What are the IPC-7351B PCB Footprint dimensions for C19397197?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C19397197 (UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 49 copper pads plus a central exposed thermal pad (EPAD) of 5.60 × 5.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C19397197?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C19397197 (Semiconductor, UFQFPN-48_L7.0-W7.0-P0.50-BL-EP5.6) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (49 pins) & STM32W108 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VDD_24MHZPower_InPrimary positive power supply input (VDD_24MHZ) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2VDD_VCOPower_InPrimary positive power supply input (VDD_VCO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3RF_PDigital_IOSignal terminal RF_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RF_P. Supported peripheral buses: General.
4RF_NDigital_IOSignal terminal RF_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RF_N. Supported peripheral buses: General.
5VDD_RFPower_InPrimary positive power supply input (VDD_RF) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
6RF_TX_ALT_PDigital_IOSignal terminal RF_TX_ALT_P (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RF_TX_ALT_P. Supported peripheral buses: General.
7RF_TX_ALT_NDigital_IOSignal terminal RF_TX_ALT_N (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RF_TX_ALT_N. Supported peripheral buses: General.
8VDD_IFPower_InPrimary positive power supply input (VDD_IF) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
9BIAS_RDigital_IOSignal terminal BIAS_R (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: BIAS_R. Supported peripheral buses: General.
10VDD_PADSAPower_InPrimary positive power supply input (VDD_PADSA) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
11PC5/TX_ACTIVEDigital_IOSignal terminal PC5/TX_ACTIVE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5/TX_ACTIVE. Supported peripheral buses: General.
12nRESETDigital_IOActive-low hardware reset terminal (nRESET): pulling this pin Low resets the processor core and peripherals.
13IO15Digital_IOGPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P
14IO16Digital_IOGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15VREG_OUTPower_InPrimary positive power supply input (VREG_OUT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
16VDD_PADSPower_InPrimary positive power supply input (VDD_PADS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
17VDD_COREPower_InPrimary positive power supply input (VDD_CORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
18PA7/TIM1_CH4/REG_ENDigital_IOSignal terminal PA7/TIM1_CH4/REG_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/TIM1_CH4/REG_EN. Supported peripheral buses: PWM.
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9Digital_IOGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21PA0/TIM2_CH1/SC2MOSIDigital_IOSignal terminal PA0/TIM2_CH1/SC2MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0/TIM2_CH1/SC2MOSI. Supported peripheral buses: PWM.
22IO11Digital_IOGPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID
23VDD_PADSPower_InPrimary positive power supply input (VDD_PADS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24IO13Digital_IOGPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25IO14Digital_IOGPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26IO21Digital_IOGPIO21 / RTC_GPIO21
27IO47Digital_IOGPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF
28VDD_PADSPower_InPrimary positive power supply input (VDD_PADS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
29PA6/TIM1_CH3Digital_IOSignal terminal PA6/TIM1_CH3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/TIM1_CH3. Supported peripheral buses: PWM.
30IO30Digital_IOGeneral Purpose Digital I/O Pin IO30
31IO31Digital_IOGeneral Purpose Digital I/O Pin IO31
32SWCLK/JTCKDigital_IOSignal terminal SWCLK/JTCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SWCLK/JTCK. Supported peripheral buses: SWD/JTAG.
33PC2/JTDO/SWODigital_IOSignal terminal PC2/JTDO/SWO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2/JTDO/SWO. Supported peripheral buses: SWD/JTAG.
34PC3/JTDIDigital_IOSignal terminal PC3/JTDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3/JTDI. Supported peripheral buses: SWD/JTAG.
35PC4/JTMS/SWDIODigital_IOSignal terminal PC4/JTMS/SWDIO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4/JTMS/SWDIO. Supported peripheral buses: SWD/JTAG.
36IO36Digital_IOGeneral Purpose Digital I/O Pin IO36
37VDD_PADSPower_InPrimary positive power supply input (VDD_PADS) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
38IO38Digital_IOGeneral Purpose Digital I/O Pin IO38
39VDD_MEMPower_InPrimary positive power supply input (VDD_MEM) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
40IO40Digital_IOGeneral Purpose Digital I/O Pin IO40
41PB7/ADC2/IRQC/TIM1_CH2Digital_IOSignal terminal PB7/ADC2/IRQC/TIM1_CH2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/ADC2/IRQC/TIM1_CH2. Supported peripheral buses: ADC, PWM.
42PB6/ADC1/IRQB/TIM1_CH1Digital_IOSignal terminal PB6/ADC1/IRQB/TIM1_CH1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/ADC1/IRQB/TIM1_CH1. Supported peripheral buses: ADC, PWM.
43IO43Digital_IOGeneral Purpose Digital I/O Pin IO43
44VDD_COREPower_InPrimary positive power supply input (VDD_CORE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
45VDD_PREPower_InPrimary positive power supply input (VDD_PRE) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
46VDD_SYNTHPower_InPrimary positive power supply input (VDD_SYNTH) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
47OSC_INDigital_IOSignal terminal OSC_IN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK.
48OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
49GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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