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CH32V305GBU6 (QFN-28(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH32V305GBU6

WCHID: C19100608QFN-28(4x4) · 29 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH32V305GBU6 (QFN-28(4x4))1VBAT2OSC_OUT/PD13NRST4PC25PC36OSC_OUT7PA1（15）8PA5/SPI1SCK9PA6/SPI1MISO10PA7/SPI1MOSI11PB10/UART3TX12PB11/UART3RX13PB12/SPI2NSS14IO1615PB14/SPI2MIS29GND28PB7/USB2DP/U27PB6/USB2DM/U26PD2/UART5RX/25IO1424IO1323PA722PA621PA5（15）20PA419V_DD418V_SS417PA316PB15/SPI2MOSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
2OSC_OUT/PD1I/OMultiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)
3NRSTISystem Enable & Hardware Reset (NRST)
4PC2I/OMultiplexed I/O & Peripheral Pin PC2 (UART, ADC, PWM)
5PC3I/OMultiplexed I/O & Peripheral Pin PC3 (UART, ADC)
6OSC_OUTI/OMultiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)
7PA1（15）I/OMultiplexed I/O & Peripheral Pin PA1（15） (UART, ADC, PWM)
8PA5/SPI1SCKI/OMultiplexed I/O & Peripheral Pin PA5/SPI1SCK (SPI)
9PA6/SPI1MISOI/OMultiplexed I/O & Peripheral Pin PA6/SPI1MISO (SPI)
10PA7/SPI1MOSII/OMultiplexed I/O & Peripheral Pin PA7/SPI1MOSI (SPI)
11PB10/UART3TX/I2C2SCLI/OMultiplexed I/O & Peripheral Pin PB10/UART3TX/I2C2SCL (UART, I2C)
12PB11/UART3RX/I2C2SDAI/OMultiplexed I/O & Peripheral Pin PB11/UART3RX/I2C2SDA (UART, I2C)
13PB12/SPI2NSS/CAN2RXI/OMultiplexed I/O & Peripheral Pin PB12/SPI2NSS/CAN2RX (SPI, CAN)
14IO16I/OGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15PB14/SPI2MISO/UART3RTSI/OMultiplexed I/O & Peripheral Pin PB14/SPI2MISO/UART3RTS (UART, SPI)
16PB15/SPI2MOSI/UART1TX2I/OMultiplexed I/O & Peripheral Pin PB15/SPI2MOSI/UART1TX2 (UART, SPI)
17PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
18V_SS4I/OMultiplexed I/O & Peripheral Pin V_SS4 (General)
19V_DD4I/OMultiplexed I/O & Peripheral Pin V_DD4 (General)
20PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC, PWM)
21PA5（15）I/OMultiplexed I/O & Peripheral Pin PA5（15） (DAC)
22PA6I/OMultiplexed I/O & Peripheral Pin PA6 (ADC, PWM)
23PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, PWM)
24IO13I/OGPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25IO14I/OGPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26PD2/UART5RX/SD_CMDI/OMultiplexed I/O & Peripheral Pin PD2/UART5RX/SD_CMD (UART)
27PB6/USB2DM/UART1TX1I/OMultiplexed I/O & Peripheral Pin PB6/USB2DM/UART1TX1 (USB, UART)
28PB7/USB2DP/UART1RX1I/OMultiplexed I/O & Peripheral Pin PB7/USB2DP/UART1RX1 (USB, UART)
29GNDGNDGround Reference Pin (GND)
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)
Design note: VBAT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH32V305GBU6 (WCH · QFN-28(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH32V305GBU6 (QFN-28(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH32V305GBU6 (QFN-28(4x4)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH32V305GBU6 (QFN-28(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH32V305GBU6 (QFN-28(4x4)) - 4. Package Dimensions (D×E×A)
QFN-28(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH32V305GBU6 (QFN-28(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH32V305GBU6 (QFN-28(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)
Showing 1–9 of 9 uncropped original figures for CH32V208 / CH32V305 / CH32V307
P5 · p05_fig011226×1550px
CH32V305GBU6 (QFN-28(4x4)) — V3.9 4
V3.9 4
P20 · p20_fig011472×899px
CH32V305GBU6 (QFN-28(4x4)) — PA14/SWCLK 49 PA15 50 PC10 51 PC11 52 PC12 53 PD2 54 PB3 55 PB4 56 PB5 57 PB6/USB2DM 58 PB7/USB2DP 59 BOOT0 60 PB8 61 PB9 62 VSS_3 63 VIO_3 64
PA14/SWCLK 49 PA15 50 PC10 51 PC11 52 PC12 53 PD2 54 PB3 55 PB4 56 PB5 57 PB6/USB2DM 58 PB7/USB2DP 59 BOOT0 60 PB8 61 PB9 62 VSS_3 63 VIO_3 64
P20 · p20_fig01P20
CH32V305GBU6 (QFN-28(4x4)) — Datasheet Page 20 (p20_fig01)
Datasheet Page 20 (p20_fig01)
P21 · p21_fig011757×906px
CH32V305GBU6 (QFN-28(4x4)) — CH32V305GBU6
CH32V305GBU6
P21 · p21_fig01P21
CH32V305GBU6 (QFN-28(4x4)) — Datasheet Page 21 (p21_fig01)
Datasheet Page 21 (p21_fig01)
P35 · p35_fig011776×925px
CH32V305GBU6 (QFN-28(4x4)) — 寄存器相应位配置为11b。 注14：TIM2_CH1 和TIM2_ETR 共用一个引脚，但不能同时使用。 注15、注16：对于CH32V305FBP6芯片，PA5和PA1引脚在芯片内部短接合封，禁止将两个IO均配置为输出
寄存器相应位配置为11b。 注14：TIM2_CH1 和TIM2_ETR 共用一个引脚，但不能同时使用。 注15、注16：对于CH32V305FBP6芯片，PA5和PA1引脚在芯片内部短接合封，禁止将两个IO均配置为输出
P35 · p35_fig021589×1313px
CH32V305GBU6 (QFN-28(4x4)) — V3.9 34
V3.9 34
P55 · p55_fig01588×896px
CH32V305GBU6 (QFN-28(4x4)) — 图4-2-2 CH32V317 电流消耗测量
图4-2-2 CH32V317 电流消耗测量
P56 · p56_fig011852×377px
CH32V305GBU6 (QFN-28(4x4)) — 符号 参数 条件 典型值 单位 使能所有外设 关闭所有外设
符号 参数 条件 典型值 单位 使能所有外设 关闭所有外设

Technical Specifications & Part Details (CH32V305GBU6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:CH32V305GBU6 (QFN-28(4x4)) is a 28-pin embedded microcontroller unit (mcu) featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
25MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-28(4x4))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, CAN, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.80×2.80mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-28(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH32V305GBU6 (QFN-28(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH32V305GBU6 (QFN-28(4x4))?

Manufactured by WCH, the CH32V305GBU6 is housed in a QFN-28(4x4) package with 29 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V / 5.0V Standard Logic)), 2 (OSC_OUT/PD1: Multiplexed I/O & Peripheral Pin OSC_OUT/PD1 (RTC/CLK)), 3 (NRST: System Enable & Hardware Reset (NRST)), 4 (PC2: Multiplexed I/O & Peripheral Pin PC2 (UART, ADC, PWM)), 5 (PC3: Multiplexed I/O & Peripheral Pin PC3 (UART, ADC)), 6 (OSC_OUT: Multiplexed I/O & Peripheral Pin OSC_OUT (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for CH32V305GBU6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH32V305GBU6 (QFN-28(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 2.80 × 2.80 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH32V305GBU6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH32V305GBU6 (WCH, QFN-28(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & CH32V208 / CH32V305 / CH32V307 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
2OSC_OUT/PD1Digital_IOSignal terminal OSC_OUT/PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT/PD1. Supported peripheral buses: RTC/CLK.
3NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
4PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: UART, ADC, PWM.
5PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: UART, ADC.
6OSC_OUTDigital_IOSignal terminal OSC_OUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK.
7PA1（15）Digital_IOSignal terminal PA1（15） (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1（15）. Supported peripheral buses: UART, ADC, PWM.
8PA5/SPI1SCKDigital_IOSignal terminal PA5/SPI1SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5/SPI1SCK. Supported peripheral buses: SPI.
9PA6/SPI1MISODigital_IOSignal terminal PA6/SPI1MISO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6/SPI1MISO. Supported peripheral buses: SPI.
10PA7/SPI1MOSIDigital_IOSignal terminal PA7/SPI1MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7/SPI1MOSI. Supported peripheral buses: SPI.
11PB10/UART3TX/I2C2SCLDigital_IOSignal terminal PB10/UART3TX/I2C2SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB10/UART3TX/I2C2SCL. Supported peripheral buses: UART, I2C.
12PB11/UART3RX/I2C2SDADigital_IOSignal terminal PB11/UART3RX/I2C2SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB11/UART3RX/I2C2SDA. Supported peripheral buses: UART, I2C.
13PB12/SPI2NSS/CAN2RXDigital_IOSignal terminal PB12/SPI2NSS/CAN2RX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB12/SPI2NSS/CAN2RX. Supported peripheral buses: SPI, CAN.
14IO16Digital_IOGPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N
15PB14/SPI2MISO/UART3RTSDigital_IOSignal terminal PB14/SPI2MISO/UART3RTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB14/SPI2MISO/UART3RTS. Supported peripheral buses: UART, SPI.
16PB15/SPI2MOSI/UART1TX2Digital_IOSignal terminal PB15/SPI2MOSI/UART1TX2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB15/SPI2MOSI/UART1TX2. Supported peripheral buses: UART, SPI.
17PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
18V_SS4Digital_IOSignal terminal V_SS4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V_SS4. Supported peripheral buses: General.
19V_DD4Digital_IOSignal terminal V_DD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: V_DD4. Supported peripheral buses: General.
20PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, DAC, PWM.
21PA5（15）Digital_IOSignal terminal PA5（15） (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5（15）. Supported peripheral buses: DAC.
22PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: ADC, PWM.
23PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, PWM.
24IO13Digital_IOGPIO13 / RTC_GPIO13 / TOUCH13 / ADC2_CH2 / FSPIQ
25IO14Digital_IOGPIO14 / RTC_GPIO14 / TOUCH14 / ADC2_CH3 / FSPIWP
26PD2/UART5RX/SD_CMDDigital_IOSignal terminal PD2/UART5RX/SD_CMD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2/UART5RX/SD_CMD. Supported peripheral buses: UART.
27PB6/USB2DM/UART1TX1Digital_IOSignal terminal PB6/USB2DM/UART1TX1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6/USB2DM/UART1TX1. Supported peripheral buses: USB, UART.
28PB7/USB2DP/UART1RX1Digital_IOSignal terminal PB7/USB2DP/UART1RX1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7/USB2DP/UART1RX1. Supported peripheral buses: USB, UART.
29GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
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