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AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — Symbol, Footprint IPC-7351B & 3D STEP Model

AVR128DA64T-E/MR

MICROCHIPID: C1870725VQFN-64-EP(9x9) · 65 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AVR128DA64T-E/MR (VQFN-64-EP(9x9))1PA32PA43PA54PA65PA76VDD7Bit8PB09PB110PB211Default12PB413PB514PB615PB716PC017PC118PC219PC320VDD21GND22PC423PC524PC625PC726PDO27PD128PD229PD330PD431PD532PD633PD765EP64PA263PA162PA0(EXTCLK)61PG760PG659PG558PG457GND56VDD55PG354PG253PG152PG051UPDI50PF6(RESET#)49PF548PF447PF346PF245PF144PF043PE742PE641PE540PE439PE338PE237PE136PE035GND34AVDDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.848.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465E=9.00mm · Pitch e=0.50mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (65/65)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
2PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
4PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
5PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
6VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
7BitI/OMultiplexed I/O & Peripheral Pin Bit (General)
8PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
9PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
10PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
11DefaultI/OMultiplexed I/O & Peripheral Pin Default (General)
12PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
13PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
14PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
15PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
16PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
17PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
18PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
19PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
20VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
21GNDGNDGround Reference Pin (GND)
22PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
23PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
24PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
25PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
26PDOI/OMultiplexed I/O & Peripheral Pin PDO (General)
27PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
28PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
29PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
30PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
31PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
32PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
33PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
34AVDDPowerPower Supply Input (AVDD — 3.3V / 5.0V Standard Logic)
35GNDGNDGround Reference Pin (GND)
36PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
37PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
38PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
39PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
40PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
41PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
42PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
43PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
44PF0I/OMultiplexed I/O & Peripheral Pin PF0 (General)
45PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
46PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
47PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
48PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
49PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
50PF6(RESET#)ISystem Enable & Hardware Reset (PF6(RESET#))
51UPDII/OMultiplexed I/O & Peripheral Pin UPDI (General)
52PG0I/OMultiplexed I/O & Peripheral Pin PG0 (General)
53PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
54PG2I/OMultiplexed I/O & Peripheral Pin PG2 (General)
55PG3I/OMultiplexed I/O & Peripheral Pin PG3 (General)
56VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
57GNDGNDExposed Thermal & Ground Pad (GND)
58PG4I/OMultiplexed I/O & Peripheral Pin PG4 (General)
59PG5I/OMultiplexed I/O & Peripheral Pin PG5 (General)
60PG6I/OMultiplexed I/O & Peripheral Pin PG6 (General)
61PG7I/OMultiplexed I/O & Peripheral Pin PG7 (General)
62PA0(EXTCLK)I/OMultiplexed I/O & Peripheral Pin PA0(EXTCLK) (General)
63PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
64PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
65EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 PA3
I/O
Multiplexed I/O & Peripheral Pin PA3 (General)
Design note: Signal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 10 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AVR128DA64T-E/MR (MICROCHIP · VQFN-64-EP(9x9))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) - 2. Standard Pinout (Top View)
True package pinout (65 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) - 4. Package Dimensions (D×E×A)
VQFN-64-EP(9x9) · 9.00×9.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) - 5. Recommended Land Pattern
IPC-7351B Footprint (65 Pads)Expand ›
6. Application SchematicSCHEMATIC
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (10 figures · Page 1/1)
Showing 1–10 of 10 uncropped original figures for AVR128
P1 · p01_fig03EXACT PACKAGE
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — Figure 2. AVR® DA Device Designations
Figure 2. AVR® DA Device Designations
P1 · p01_fig01456×280px
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — Introduction
Introduction
P1 · p01_fig021575×631px
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — Figure 1. AVR® DA Family Overview
Figure 1. AVR® DA Family Overview
P586 · p586_fig011268×1117px
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — MILLIMETERS
MILLIMETERS
P597 · p597_fig011127×1596px
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M
Pin 1 visual index feature may vary, but must be located within the hatched area. Package is saw singulated Dimensioning and tolerancing per ASME Y14.5M
P597 · p597_fig01P597
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — Datasheet Page 597 (p597_fig01)
Datasheet Page 597 (p597_fig01)
P598 · p598_fig011191×1384px
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — C2
C2
P598 · p598_fig01P598
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — Datasheet Page 598 (p598_fig01)
Datasheet Page 598 (p598_fig01)
P600 · p600_fig011645×1697px
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — 64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]
P601 · p601_fig011053×855px
AVR128DA64T-E/MR (VQFN-64-EP(9x9)) — RECOMMENDED LAND PATTERN
RECOMMENDED LAND PATTERN

Technical Specifications & Part Details (AVR128DA64T-E/MR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AVR128DA64T-E/MR (VQFN-64-EP(9x9)) is a 64-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 0.90 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C to +85°C with integrated UART, SPI, I2C, ADC, DAC interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
24 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 0.90 mm (A1=0.03 mm)
Package family: QFN (VQFN-64-EP(9x9))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, DAC
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol65 auto-grouped pins
OK
IPC-7351B Land Pattern65 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 7.30×7.30mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (VQFN-64-EP(9x9))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.90mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
65P / 65Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
VQFN-64-EP(9x9)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AVR128DA64T-E/MR (VQFN-64-EP(9x9))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AVR128DA64T-E/MR (VQFN-64-EP(9x9))?

Manufactured by MICROCHIP, the AVR128DA64T-E/MR is housed in a VQFN-64-EP(9x9) package with 65 pins and a 0.50 mm lead pitch. Key pins include: 1 (PA3: Multiplexed I/O & Peripheral Pin PA3 (General)), 2 (PA4: Multiplexed I/O & Peripheral Pin PA4 (General)), 3 (PA5: Multiplexed I/O & Peripheral Pin PA5 (General)), 4 (PA6: Multiplexed I/O & Peripheral Pin PA6 (General)), 5 (PA7: Multiplexed I/O & Peripheral Pin PA7 (General)), 6 (VDD: Power Supply Input (VDD — 3.3V / 5.0V Standard Logic)).

What are the IPC-7351B PCB Footprint dimensions for AVR128DA64T-E/MR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AVR128DA64T-E/MR (VQFN-64-EP(9x9)) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.50 mm, and 65 copper pads plus a central exposed thermal pad (EPAD) of 7.30 × 7.30 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AVR128DA64T-E/MR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AVR128DA64T-E/MR (MICROCHIP, VQFN-64-EP(9x9)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (65 pins) & AVR128 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PA3Digital_IOSignal terminal PA3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
2PA4Digital_IOSignal terminal PA4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
3PA5Digital_IOSignal terminal PA5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
4PA6Digital_IOSignal terminal PA6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
5PA7Digital_IOSignal terminal PA7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
7BitDigital_IOSignal terminal Bit (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Bit. Supported peripheral buses: General.
8PB0Digital_IOSignal terminal PB0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
9PB1Digital_IOSignal terminal PB1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
10PB2Digital_IOSignal terminal PB2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
11DefaultDigital_IOSignal terminal Default (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Default. Supported peripheral buses: General.
12PB4Digital_IOSignal terminal PB4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
13PB5Digital_IOSignal terminal PB5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
14PB6Digital_IOSignal terminal PB6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
15PB7Digital_IOSignal terminal PB7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
16PC0Digital_IOSignal terminal PC0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
17PC1Digital_IOSignal terminal PC1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
18PC2Digital_IOSignal terminal PC2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
19PC3Digital_IOSignal terminal PC3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
20VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
22PC4Digital_IOSignal terminal PC4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
23PC5Digital_IOSignal terminal PC5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
24PC6Digital_IOSignal terminal PC6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
25PC7Digital_IOSignal terminal PC7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
26PDODigital_IOSignal terminal PDO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PDO. Supported peripheral buses: General.
27PD1Digital_IOSignal terminal PD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
28PD2Digital_IOSignal terminal PD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
29PD3Digital_IOSignal terminal PD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
30PD4Digital_IOSignal terminal PD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
31PD5Digital_IOSignal terminal PD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
32PD6Digital_IOSignal terminal PD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
33PD7Digital_IOSignal terminal PD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
34AVDDPower_InPrimary positive power supply input (AVDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
35GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
36PE0Digital_IOSignal terminal PE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
37PE1Digital_IOSignal terminal PE1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
38PE2Digital_IOSignal terminal PE2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
39PE3Digital_IOSignal terminal PE3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
40PE4Digital_IOSignal terminal PE4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
41PE5Digital_IOSignal terminal PE5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
42PE6Digital_IOSignal terminal PE6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
43PE7Digital_IOSignal terminal PE7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
44PF0Digital_IOSignal terminal PF0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General.
45PF1Digital_IOSignal terminal PF1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
46PF2Digital_IOSignal terminal PF2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
47PF3Digital_IOSignal terminal PF3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
48PF4Digital_IOSignal terminal PF4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
49PF5Digital_IOSignal terminal PF5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
50PF6(RESET#)Digital_IOActive-low hardware reset terminal (PF6(RESET#)): pulling this pin Low resets the processor core and peripherals.
51UPDIDigital_IOSignal terminal UPDI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UPDI. Supported peripheral buses: General.
52PG0Digital_IOSignal terminal PG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG0. Supported peripheral buses: General.
53PG1Digital_IOSignal terminal PG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG1. Supported peripheral buses: General.
54PG2Digital_IOSignal terminal PG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG2. Supported peripheral buses: General.
55PG3Digital_IOSignal terminal PG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG3. Supported peripheral buses: General.
56VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
57GNDGNDBottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
58PG4Digital_IOSignal terminal PG4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG4. Supported peripheral buses: General.
59PG5Digital_IOSignal terminal PG5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG5. Supported peripheral buses: General.
60PG6Digital_IOSignal terminal PG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG6. Supported peripheral buses: General.
61PG7Digital_IOSignal terminal PG7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PG7. Supported peripheral buses: General.
62PA0(EXTCLK)Digital_IOSignal terminal PA0(EXTCLK) (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA0(EXTCLK). Supported peripheral buses: General.
63PA1Digital_IOSignal terminal PA1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
64PA2Digital_IOSignal terminal PA2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
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