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STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L562MEY6QTR

STID: C1857435WLCSP-81(4.1x4.4) · 81 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L562MEY6QTR (WLCSP-81(4.1x4.4))A1PE5A2PE3A3PD2A4PG13A5VDDIO2A6PB5A7PB9A8V15SMPS_2A9VDDB1VDDUSBB2PE4B3PE2B4PG12B5VSSB6PB4B7PC13B8VSSB9VBATC1PA11C2PA12C3PC11C4PG10C5PG15C6PB6C7PB8C8IOC8C9PC14 - OSC3_D1PA9D2PA13D3PF3D4PG9D5PG14D6PB7D7PH3-BOOT0D8PH1 - OSC_ OD9PH0 - OSC_I E1PF2E2PC7E3PF4E4PA15E5PG11J9VSSJ8VDDJ7PA7J6PB0J5PB2J4PB10J3VDDSMPSJ2VSSSMPSJ1V15SMPS_1H9VDDAH8PA0H7PA4H6PA5H5PB1H4PB11H3VLXSMPSH2VSSH1VDDG9VSSA/ VREF -G8VREF +G7PC3G6PA2G5PA6G4PC4G3PC9G2PB12G1PB14F9VDDF8PC1F7PC2F6PA1F5PA3F4PA8F3PC8F2PF5F1PB15E9NRSTE8VSSE7PC0E6PB3Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.858.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1A2B2C2D2E2F2G2H2J2A3B3C3D3E3F3G3H3J3A4B4C4D4E4F4G4H4J4A5B5C5D5E5F5G5H5J5A6B6C6D6E6F6G6H6J6A7B7C7D7E7F7G7H7J7A8B8C8D8E8F8G8H8J8A9B9C9D9E9F9G9H9J9E=4.10mm · Pitch e=0.40mmD=4.40mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.10mm × 4.40mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (81/81)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PE5I/OMultiplexed I/O & Peripheral Pin PE5 (SPI)
A2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
A3PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
A4PG13I/OMultiplexed I/O & Peripheral Pin PG13 (General)
A5VDDIO2PowerPower Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))
A6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
A7PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
A8V15SMPS_2I/OMultiplexed I/O & Peripheral Pin V15SMPS_2 (General)
A9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B1VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
B2PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
B3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
B4PG12I/OMultiplexed I/O & Peripheral Pin PG12 (General)
B5VSSGNDGround Reference Pin (VSS)
B6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B7PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
B8VSSGNDGround Reference Pin (VSS)
B9VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
C2PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C3PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
C4PG10I/OMultiplexed I/O & Peripheral Pin PG10 (General)
C5PG15I/OMultiplexed I/O & Peripheral Pin PG15 (General)
C6PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
C7PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
C8IOC8I/OGeneral Purpose Digital I/O Pin IOC8
C9PC14 - OSC3_2IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14 - OSC3_2IN (PC14) (RTC/CLK)
D1PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
D2PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
D3PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
D4PG9I/OMultiplexed I/O & Peripheral Pin PG9 (General)
D5PG14I/OMultiplexed I/O & Peripheral Pin PG14 (General)
D6PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
D7PH3-BOOT0I/OMultiplexed I/O & Peripheral Pin PH3-BOOT0 (General)
D8PH1 - OSC_ OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1 - OSC_ OUT (PH1) (RTC/CLK)
D9PH0 - OSC_I N (PH0)I/OMultiplexed I/O & Peripheral Pin PH0 - OSC_I N (PH0) (RTC/CLK)
E1PF2I/OMultiplexed I/O & Peripheral Pin PF2 (I2C)
E2PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
E3PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
E4PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
E5PG11I/OMultiplexed I/O & Peripheral Pin PG11 (General)
E6PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
E7PC0I/OMultiplexed I/O & Peripheral Pin PC0 (I2C, ADC)
E8VSSGNDGround Reference Pin (VSS)
E9NRSTISystem Enable & Hardware Reset (NRST)
F1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
F2PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
F3PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F4PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
F5PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM)
F6PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, SPI, I2C, ADC, PWM)
F7PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
F8PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC)
F9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G1PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
G2PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
G3PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
G4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
G5PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC, PWM)
G6PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
G7PC3I/OMultiplexed I/O & Peripheral Pin PC3 (I2C, ADC)
G8VREF +AnalogMultiplexed I/O & Peripheral Pin VREF + (General)
G9VSSA/ VREF -GNDGround Reference Pin (VSSA/ VREF -)
H1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
H2VSSGNDGround Reference Pin (VSS)
H3VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
H4PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
H5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM)
H6PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM)
H7PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
H8PA0I/OMultiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM)
H9VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
J1V15SMPS_1I/OMultiplexed I/O & Peripheral Pin V15SMPS_1 (General)
J2VSSSMPSGNDGround Reference Pin (VSSSMPS)
J3VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
J4PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
J5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK)
J6PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM)
J7PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, I2C, ADC, PWM)
J8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
J9VSSGNDGround Reference Pin (VSS)
PIN A1 PE5
I/O
Multiplexed I/O & Peripheral Pin PE5 (SPI)
Design note: Alt: TRACED2 TIM3 CH3 ,_ , SAI1_CK2 , DFSDM1_CKIN3 , TSC_G7IO4_ , FMC_A21 , SAI1_SCKA_ , EVENTOUT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 33 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L562MEY6QTR (ST · WLCSP-81(4.1x4.4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) - 2. Standard Pinout (Top View)
True package pinout (81 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) - 4. Package Dimensions (D×E×A)
WLCSP-81(4.1x4.4) · 4.10×4.40mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (81 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (33 figures · Page 1/3)
Showing 1–12 of 33 uncropped original figures for STM32L562
P84 · p84_fig01EXACT PACKAGE
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Figure 16. STM32L562xxxxP LQFP64 external SMPS pinout
Figure 16. STM32L562xxxxP LQFP64 external SMPS pinout
P84 · p84_fig02EXACT PACKAGE
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — PA0
PA0
P85 · p85_fig01EXACT PACKAGE
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Figure 18. STM32L562xxxxP WLCSP81 external SMPS ballout
Figure 18. STM32L562xxxxP WLCSP81 external SMPS ballout
P319 · p319_fig01EXACT PACKAGE
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Figure 85. WLCSP81 outline
Figure 85. WLCSP81 outline
P320 · p320_fig01EXACT PACKAGE
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Figure 86. WLCSP 81 recommended footprint
Figure 86. WLCSP 81 recommended footprint
P321 · p321_fig01EXACT PACKAGE
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Figure 87. Example of WLCSP81 package marking (package top view
Figure 87. Example of WLCSP81 package marking (package top view
P1 · p01_fig011751×860px
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — • 62 μA/MHz Run mode @ 3 V (SMPS step-down converter mode)
• 62 μA/MHz Run mode @ 3 V (SMPS step-down converter mode)
P85 · p85_fig01P85
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Datasheet Page 85 (p85_fig01)
Datasheet Page 85 (p85_fig01)
P141 · p141_fig011560×1866px
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Figure 27. STM32L552xx and STM32L562xx power supply overview
Figure 27. STM32L552xx and STM32L562xx power supply overview
P141 · p141_fig01P141
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Datasheet Page 141 (p141_fig01)
Datasheet Page 141 (p141_fig01)
P218 · p218_fig011546×702px
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Figure 35. Typical application with an 8 MHz crystal
Figure 35. Typical application with an 8 MHz crystal
P219 · p219_fig011546×702px
STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) — Figure 36. Typical application with a 32.768 kHz crystal
Figure 36. Typical application with a 32.768 kHz crystal
Page 1 / 3 (33 extracted figures)

Technical Specifications & Part Details (STM32L562MEY6QTR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) is a 81-pin embedded microcontroller unit (mcu) featuring a 4.40 × 4.10 × 0.56 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
110 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
25 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
4.40 × 4.10 × 0.56 mm (A1=0.18 mm)
Package family: WLCSP (WLCSP-81(4.1x4.4))
Pin Count & Lead PitchN / e
81 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3-BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol81 auto-grouped pins
OK
IPC-7351B Land Pattern81 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32L562 (10)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (WLCSP-81(4.1x4.4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.40 × 4.10 mm
Height (A) & Pitch (e)IPC-7351B
A=0.56mm · e=0.40mm
Pad Size (W × L)Level B
0.20 × 0.20 mm
Pins / Total PadsTopology
81P / 81Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-81(4.1x4.4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L562MEY6QTR (WLCSP-81(4.1x4.4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L562MEY6QTR (WLCSP-81(4.1x4.4))?

Manufactured by ST, the STM32L562MEY6QTR is housed in a WLCSP-81(4.1x4.4) package with 81 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: A1 (PE5: Multiplexed I/O & Peripheral Pin PE5 (SPI)), A2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A3 (PD2: Multiplexed I/O & Peripheral Pin PD2 (General)), A4 (PG13: Multiplexed I/O & Peripheral Pin PG13 (General)), A5 (VDDIO2: Power Supply Input (VDDIO2 — 3.3V VDD (Max 4.0V))), A6 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32L562MEY6QTR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L562MEY6QTR (WLCSP-81(4.1x4.4)) has a nominal body envelope of 4.10 × 4.40 mm, pitch e = 0.40 mm, and 81 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L562MEY6QTR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L562MEY6QTR (ST, WLCSP-81(4.1x4.4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (81 pins) & STM32L562 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: SPI.
A2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
A3PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
A4PG13Digital_IOSignal terminal PG13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: General.
A5VDDIO2Power_InPrimary positive power supply input (VDDIO2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
A7PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
A8V15SMPS_2Digital_IOSignal terminal V15SMPS_2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: V15SMPS_2. Supported peripheral buses: General.
A9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B2PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
B4PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: General.
B5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B7PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
B8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
B9VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
C2PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C3PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
C4PG10Digital_IOSignal terminal PG10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: General.
C5PG15Digital_IOSignal terminal PG15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG15. Supported peripheral buses: General.
C6PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
C7PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
C8IOC8Digital_IOGeneral Purpose Digital I/O Pin IOC8
C9PC14 - OSC3_2IN (PC14)Digital_IOSignal terminal PC14 - OSC3_2IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC3_2IN (PC14). Supported peripheral buses: RTC/CLK.
D1PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
D2PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
D3PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
D4PG9Digital_IOSignal terminal PG9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG9. Supported peripheral buses: General.
D5PG14Digital_IOSignal terminal PG14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: General.
D6PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
D7PH3-BOOT0Digital_IOSignal terminal PH3-BOOT0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH3-BOOT0. Supported peripheral buses: General.
D8PH1 - OSC_ OUT (PH1)Digital_IOSignal terminal PH1 - OSC_ OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_ OUT (PH1). Supported peripheral buses: RTC/CLK.
D9PH0 - OSC_I N (PH0)Digital_IOSignal terminal PH0 - OSC_I N (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_I N (PH0). Supported peripheral buses: RTC/CLK.
E1PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: I2C.
E2PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
E3PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
E4PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
E5PG11Digital_IOSignal terminal PG11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG11. Supported peripheral buses: General.
E6PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
E7PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL. Supported peripheral buses: I2C, ADC.
E8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E9NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F1PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
F2PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
F3PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
F4PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
F5PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM.
F6PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_SCK. Supported peripheral buses: UART, SPI, I2C, ADC, PWM.
F7PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
F8PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI, I2C3_SDA. Supported peripheral buses: SPI, I2C, ADC.
F9VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
G1PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
G2PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
G3PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
G4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC.
G5PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC, PWM.
G6PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
G7PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: I2C, ADC.
G8VREF +AnalogSignal terminal VREF + (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF +. Supported peripheral buses: General.
G9VSSA/ VREF -GND0V electrical ground return terminal (VSSA/ VREF -) for internal core logic, I/O drivers, and analog sub-blocks.
H1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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