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STM32F405OEY6TR (WLCSP-90(4x4.2)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F405OEY6TR

STWLCSP-90(4x4.2) · 90 Pins · Pitch 0.40mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F405OEY6TR (WLCSP-90(4x4.2))A1VDDA2PA14 (JTCK/SA3PC12A4PD4A5PD7A6PB4 (NJTRST)A7BOOT0A8PDR_ONA9PC13A10VBATB1VCAP_2B2PI1B3PA15 (JTDI)B4PD2B5PD6B6PB3 (JTDO/ TB7PB7B8VDDB9PC15/ OSC32_B10PC14/OSC32_IC1PA11C2PA12C3PI0C4PC11C5PD1C6PD5C7PB6C8PB9C9VSSC10PA0/WKUP (PAD1PA8D2PA9D3PA10D4PA13 (JTMSSWD5PC10D6PD0D7PB5D8PB8D9BYPASS_REGD10PC2E1PC7E2PC8E3PC9E4VDDE5VSSJ10PA2J9PA4J8PA7J7PB2/BOOT1 (PJ6PE9J5PE11J4PB11J3PB12J2PB14J1PB13H10VSSAH9PA3H8PA6H7PB1H6PE8H5PE12H4PB10H3PD9H2PD8H1PB15G10NRSTG9VDDAG8PA5G7PB0G6PE7G5PE13G4PE15G3PD10G2PD12G1PD11F10PH0/OSC_IN (F9PH1/OSC_OUT F8PA1F7VDDF6PE10F5PE14F4VCAP_1F3PC6F2PD14F1PD15E10PC0E9PC3E8VSSE7VSSE6VDDGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.863.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1A2B2C2D2E2F2G2H2J2A3B3C3D3E3F3G3H3J3A4B4C4D4E4F4G4H4J4A5B5C5D5E5F5G5H5J5A6B6C6D6E6F6G6H6J6A7B7C7D7E7F7G7H7J7A8B8C8D8E8F8G8H8J8A9B9C9D9E9F9G9H9J9A10B10C10D10E10F10G10H10J10E=4.20mm · Pitch e=0.40mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.20mm × 4.00mm · Pitch: 0.40mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (90/90)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
A2PA14 (JTCK/SWCLK)I/OMultiplexed I/O & Peripheral Pin PA14 (JTCK/SWCLK) (SWD/JTAG)
A3PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
A4PD4I/OMultiplexed I/O & Peripheral Pin PD4 (UART)
A5PD7I/OMultiplexed I/O & Peripheral Pin PD7 (UART)
A6PB4 (NJTRST)I/OMultiplexed I/O & Peripheral Pin PB4 (NJTRST) (SPI, SWD/JTAG)
A7BOOT0IInput-Only Pin BOOT0 (General)
A8PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
A9PC13I/OMultiplexed I/O & Peripheral Pin PC13 (RTC/CLK)
A10VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B1VCAP_2I/OMultiplexed I/O & Peripheral Pin VCAP_2 (General)
B2PI1I/OMultiplexed I/O & Peripheral Pin PI1 (SPI)
B3PA15 (JTDI)I/OMultiplexed I/O & Peripheral Pin PA15 (JTDI) (SPI, PWM, SWD/JTAG)
B4PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
B5PD6I/OMultiplexed I/O & Peripheral Pin PD6 (UART)
B6PB3 (JTDO/ TRACESWO)I/OMultiplexed I/O & Peripheral Pin PB3 (JTDO/ TRACESWO) (SPI, SWD/JTAG)
B7PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C)
B8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
B9PC15/ OSC32_OUT (PC15)I/OMultiplexed I/O & Peripheral Pin PC15/ OSC32_OUT (PC15) (RTC/CLK)
B10PC14/OSC32_IN (PC14)I/OMultiplexed I/O & Peripheral Pin PC14/OSC32_IN (PC14) (RTC/CLK)
C1PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, CAN)
C2PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, CAN)
C3PI0I/OMultiplexed I/O & Peripheral Pin PI0 (SPI)
C4PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART, SPI)
C5PD1I/OMultiplexed I/O & Peripheral Pin PD1 (CAN)
C6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
C7PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C, CAN)
C8PB9I/OMultiplexed I/O & Peripheral Pin PB9 (SPI, I2C, CAN)
C9VSSGNDGround Reference Pin (VSS)
C10PA0/WKUP (PA0)I/OMultiplexed I/O & Peripheral Pin PA0/WKUP (PA0) (UART, ADC)
D1PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, I2C, RTC/CLK)
D2PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C)
D3PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
D4PA13 (JTMSSWDIO) -I/OMultiplexed I/O & Peripheral Pin PA13 (JTMSSWDIO) - (SWD/JTAG)
D5PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
D6PD0I/OMultiplexed I/O & Peripheral Pin PD0 (CAN)
D7PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C, PWM, CAN)
D8PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, I2C, CAN)
D9BYPASS_REGI/OMultiplexed I/O & Peripheral Pin BYPASS_REG (General)
D10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
E1PC7I/OMultiplexed I/O & Peripheral Pin PC7 (UART)
E2PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART)
E3PC9I/OMultiplexed I/O & Peripheral Pin PC9 (I2C, RTC/CLK)
E4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E5VSSGNDGround Reference Pin (VSS)
E6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E7VSSGNDGround Reference Pin (VSS)
E8VSSGNDGround Reference Pin (VSS)
E9PC3I/OMultiplexed I/O & Peripheral Pin PC3 (SPI, ADC)
E10PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
F1PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
F2PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
F3PC6I/OMultiplexed I/O & Peripheral Pin PC6 (UART)
F4VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
F5PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
F6PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
F7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F8PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
F9PH1/OSC_OUT (PH1)I/OMultiplexed I/O & Peripheral Pin PH1/OSC_OUT (PH1) (RTC/CLK)
F10PH0/OSC_IN (PH0)I/OMultiplexed I/O & Peripheral Pin PH0/OSC_IN (PH0) (RTC/CLK)
G1PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART)
G2PD12I/OMultiplexed I/O & Peripheral Pin PD12 (UART)
G3PD10I/OMultiplexed I/O & Peripheral Pin PD10 (UART)
G4PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
G5PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
G6PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
G7PB0I/OMultiplexed I/O & Peripheral Pin PB0 (UART, ADC)
G8PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC)
G9VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
G10NRSTISystem Enable & Hardware Reset (NRST)
H1PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI, PWM, RTC/CLK)
H2PD8I/OMultiplexed I/O & Peripheral Pin PD8 (UART)
H3PD9I/OMultiplexed I/O & Peripheral Pin PD9 (UART)
H4PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C)
H5PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
H6PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
H7PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, ADC)
H8PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC, PWM)
H9PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, ADC)
H10VSSAGNDGround Reference Pin (VSSA)
J1PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, CAN)
J2PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI)
J3PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C, CAN)
J4PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
J5PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
J6PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
J7PB2/BOOT1 (PB2)I/OMultiplexed I/O & Peripheral Pin PB2/BOOT1 (PB2) (General)
J8PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
J9PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
J10PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC)
PIN A1 VDD
Power
Power Supply Input (VDD — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 22 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F405OEY6TR (ST · WLCSP-90(4x4.2))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F405OEY6TR (WLCSP-90(4x4.2)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F405OEY6TR (WLCSP-90(4x4.2)) - 2. Standard Pinout (Top View)
True package pinout (90 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F405OEY6TR (WLCSP-90(4x4.2)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F405OEY6TR (WLCSP-90(4x4.2)) - 4. Package Dimensions (D×E×A)
WLCSP-90(4x4.2) · 4.20×4.00mm · Pitch 0.40mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F405OEY6TR (WLCSP-90(4x4.2)) - 5. Recommended Land Pattern
IPC-7351B Footprint (90 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F405OEY6TR (WLCSP-90(4x4.2)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (22 figures · Page 1/2)
Showing 1–12 of 22 uncropped original figures for STM32F405 / STM32F407
P46 · p46_fig01EXACT PACKAGE
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Figure 17. STM32F40xxx WLCSP90 ballout 2 3 4 5 6 7 8 9 10
Figure 17. STM32F40xxx WLCSP90 ballout 2 3 4 5 6 7 8 9 10
P164 · p164_fig01EXACT PACKAGE
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Figure 75. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale
Figure 75. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale
P165 · p165_fig01EXACT PACKAGE
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Figure 76. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale
Figure 76. WLCSP90 - 4.223 x 3.969 mm, 0.400 mm pitch wafer level chip scale
P166 · p166_fig01EXACT PACKAGE
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Figure 77. WLCSP90 marking example (package top view)
Figure 77. WLCSP90 marking example (package top view)
P1 · p01_fig01886×635px
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Arm® Cortex®-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM,
Arm® Cortex®-M4 32b MCU+FPU, 210DMIPS, up to 1MB Flash/192+4KB RAM,
P41 · p41_fig011546×1047px
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Figure 12. STM32F40xxx LQFP64 pinout
Figure 12. STM32F40xxx LQFP64 pinout
P46 · p46_fig01P46
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Datasheet Page 46 (p46_fig01)
Datasheet Page 46 (p46_fig01)
P77 · p77_fig011751×1451px
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Figure 21. Power supply scheme
Figure 21. Power supply scheme
P77 · p77_fig01P77
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Datasheet Page 77 (p77_fig01)
Datasheet Page 77 (p77_fig01)
P164 · p164_fig01P164
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Datasheet Page 164 (p164_fig01)
Datasheet Page 164 (p164_fig01)
P165 · p165_fig01P165
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Datasheet Page 165 (p165_fig01)
Datasheet Page 165 (p165_fig01)
P166 · p166_fig02335×192px
STM32F405OEY6TR (WLCSP-90(4x4.2)) — Revision code Date code Y WW
Revision code Date code Y WW
Page 1 / 2 (22 extracted figures)

Technical Specifications & Part Details (STM32F405OEY6TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F405OEY6TR (WLCSP-90(4x4.2)) is a 90-pin embedded microcontroller unit (mcu) featuring a 4.00 × 4.20 × 0.57 mm mechanical envelope (lead pitch e = 0.40 mm). Rated for 1.8 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, CAN, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.8 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
168 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
72 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
4.00 × 4.20 × 0.57 mm (A1=0.19 mm)
Package family: WLCSP (WLCSP-90(4x4.2))
Pin Count & Lead PitchN / e
90 Pins | Pitch e = 0.40 mm (15.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, CAN, ADC, PWM, SDIO, JTAG / SWD, IrDA, DAC, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0, PB2/BOOT1 (PB2)): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol90 auto-grouped pins
OK
IPC-7351B Land Pattern90 pads · Pitch 0.40mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32F405 / STM32F407 (20)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (WLCSP-90(4x4.2))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.20 mm
Height (A) & Pitch (e)IPC-7351B
A=0.57mm · e=0.40mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
90P / 90Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WLCSP-90(4x4.2)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F405OEY6TR (WLCSP-90(4x4.2))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F405OEY6TR (WLCSP-90(4x4.2))?

Manufactured by ST, the STM32F405OEY6TR is housed in a WLCSP-90(4x4.2) package with 90 pins and a 0.40 mm lead pitch, supporting a VCC supply range of 1.8 V to 3.6 V. Key pins include: A1 (VDD: Power Supply Input (VDD — 3.3V VDD (Max 4.0V))), A2 (PA14 (JTCK/SWCLK): Multiplexed I/O & Peripheral Pin PA14 (JTCK/SWCLK) (SWD/JTAG)), A3 (PC12: Multiplexed I/O & Peripheral Pin PC12 (UART, SPI)), A4 (PD4: Multiplexed I/O & Peripheral Pin PD4 (UART)), A5 (PD7: Multiplexed I/O & Peripheral Pin PD7 (UART)), A6 (PB4 (NJTRST): Multiplexed I/O & Peripheral Pin PB4 (NJTRST) (SPI, SWD/JTAG)).

What are the IPC-7351B PCB Footprint dimensions for STM32F405OEY6TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F405OEY6TR (WLCSP-90(4x4.2)) has a nominal body envelope of 4.20 × 4.00 mm, pitch e = 0.40 mm, and 90 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F405OEY6TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F405OEY6TR (ST, WLCSP-90(4x4.2)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (90 pins) & STM32F405 / STM32F407 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
A2PA14 (JTCK/SWCLK)Digital_IOSignal terminal PA14 (JTCK/SWCLK) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA14 (JTCK/SWCLK). Supported peripheral buses: SWD/JTAG.
A3PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI_. Supported peripheral buses: UART, SPI.
A4PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: UART.
A5PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: UART.
A6PB4 (NJTRST)Digital_IOSignal terminal PB4 (NJTRST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO, SPI1_MISO. Supported peripheral buses: SPI, SWD/JTAG.
A7BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A8PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
A9PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK.
A10VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B1VCAP_2Digital_IOSignal terminal VCAP_2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_2. Supported peripheral buses: General.
B2PI1Digital_IOSignal terminal PI1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: SPI.
B3PA15 (JTDI)Digital_IOSignal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_NSS, SPI1_NSS. Supported peripheral buses: SPI, PWM, SWD/JTAG.
B4PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
B5PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: UART.
B6PB3 (JTDO/ TRACESWO)Digital_IOSignal terminal PB3 (JTDO/ TRACESWO) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK, SPI1_SCK. Supported peripheral buses: SPI, SWD/JTAG.
B7PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C.
B8VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B9PC15/ OSC32_OUT (PC15)Digital_IOSignal terminal PC15/ OSC32_OUT (PC15) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15/ OSC32_OUT (PC15). Supported peripheral buses: RTC/CLK.
B10PC14/OSC32_IN (PC14)Digital_IOSignal terminal PC14/OSC32_IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14/OSC32_IN (PC14). Supported peripheral buses: RTC/CLK.
C1PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: UART, CAN.
C2PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: UART, CAN.
C3PI0Digital_IOSignal terminal PI0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS. Supported peripheral buses: SPI.
C4PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI.
C5PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: CAN.
C6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART.
C7PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, CAN.
C8PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_NSS, I2C1_SDA. Supported peripheral buses: SPI, I2C, CAN.
C9VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C10PA0/WKUP (PA0)Digital_IOSignal terminal PA0/WKUP (PA0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0/WKUP (PA0). Supported peripheral buses: UART, ADC.
D1PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL. Supported peripheral buses: UART, I2C, RTC/CLK.
D2PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: UART, I2C.
D3PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
D4PA13 (JTMSSWDIO) -Digital_IOSignal terminal PA13 (JTMSSWDIO) - (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMSSWDIO) -. Supported peripheral buses: SWD/JTAG.
D5PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
D6PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: CAN.
D7PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, SPI3_MOSI. Supported peripheral buses: SPI, I2C, PWM, CAN.
D8PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, CAN.
D9BYPASS_REGDigital_IOSignal terminal BYPASS_REG (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: BYPASS_REG. Supported peripheral buses: General.
D10PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: SPI, ADC.
E1PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: UART.
E2PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART.
E3PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA. Supported peripheral buses: I2C, RTC/CLK.
E4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E9PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, ADC.
E10PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
F1PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
F2PD14Digital_IOSignal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: General.
F3PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: UART.
F4VCAP_1Digital_IOSignal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
F5PE14Digital_IOSignal terminal PE14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE14. Supported peripheral buses: General.
F6PE10Digital_IOSignal terminal PE10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General.
F7VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F8PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
F9PH1/OSC_OUT (PH1)Digital_IOSignal terminal PH1/OSC_OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1/OSC_OUT (PH1). Supported peripheral buses: RTC/CLK.
F10PH0/OSC_IN (PH0)Digital_IOSignal terminal PH0/OSC_IN (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0/OSC_IN (PH0). Supported peripheral buses: RTC/CLK.
G1PD11Digital_IOSignal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD11. Supported peripheral buses: UART.
G2PD12Digital_IOSignal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: UART.
G3PD10Digital_IOSignal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: UART.
G4PE15Digital_IOSignal terminal PE15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE15. Supported peripheral buses: General.
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