ENC424J600T-I/ML (QFN-44-EP(8x8)) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of ENC424J600T-I/ML (QFN-44-EP(8x8))?

Manufactured by MICROCHIP, the ENC424J600T-I/ML is housed in a QFN-44-EP(8x8) package with 45 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (PSPMode10: Multiplexed I/O & Peripheral Pin PSPMode10 (General)), 2 (OSC2: Multiplexed I/O & Peripheral Pin OSC2 (RTC/CLK)), 3 (OSC1: Multiplexed I/O & Peripheral Pin OSC1 (RTC/CLK)), 4 (VDDOSC: Power Supply Input (VDDOSC — 3.0V to 3.6V)), 5 (AD4: Multiplexed I/O & Peripheral Pin AD4 (General)), 6 (AD5: Multiplexed I/O & Peripheral Pin AD5 (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for ENC424J600T-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ENC424J600T-I/ML (QFN-44-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.65 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 6.55 × 6.55 mm with a 60% IPC-7525 windowed solder paste grid.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ENC424J600T-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ENC424J600T-I/ML (MICROCHIP, QFN-44-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 8.00mm × 8.00mm · Pitch: 0.65mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (45/45)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	PSPMode10	I/O	Multiplexed I/O & Peripheral Pin PSPMode10 (General)
2	OSC2	I/O	Multiplexed I/O & Peripheral Pin OSC2 (RTC/CLK)
3	OSC1	I/O	Multiplexed I/O & Peripheral Pin OSC1 (RTC/CLK)
4	VDDOSC	Power	Power Supply Input (VDDOSC — 3.0V to 3.6V)
5	AD4	I/O	Multiplexed I/O & Peripheral Pin AD4 (General)
6	AD5	I/O	Multiplexed I/O & Peripheral Pin AD5 (General)
7	AD6	I/O	Multiplexed I/O & Peripheral Pin AD6 (General)
8	AD7	I/O	Multiplexed I/O & Peripheral Pin AD7 (General)
9	LEDB	I/O	Multiplexed I/O & Peripheral Pin LEDB (General)
10	LEDA	I/O	Multiplexed I/O & Peripheral Pin LEDA (General)
11	RBIAS	I/O	Multiplexed I/O & Peripheral Pin RBIAS (General)
12	VDDPLL	Power	Power Supply Input (VDDPLL — 3.0V to 3.6V)
13	VSSPLL	GND	Ground Reference Pin (VSSPLL)
14	VSSRX	GND	Ground Reference Pin (VSSRX)
15	VDDRX	Power	Power Supply Input (VDDRX — 3.0V to 3.6V)
16	TPIN+	I/O	Multiplexed I/O & Peripheral Pin TPIN+ (General)
17	TPIN -	I/O	Multiplexed I/O & Peripheral Pin TPIN - (General)
18	VDDTX	Power	Power Supply Input (VDDTX — 3.0V to 3.6V)
19	VSSTX	GND	Ground Reference Pin (VSSTX)
20	TPOUT+	I/O	Multiplexed I/O & Peripheral Pin TPOUT+ (General)
21	TPOUT -	I/O	Multiplexed I/O & Peripheral Pin TPOUT - (General)
22	VSSTX	GND	Ground Reference Pin (VSSTX)
23	CLKOUT	I/O	Multiplexed I/O & Peripheral Pin CLKOUT (General)
24	SPISEL	I/O	Multiplexed I/O & Peripheral Pin SPISEL (SPI)
25	AD8	I/O	Multiplexed I/O & Peripheral Pin AD8 (General)
26	AD9	I/O	Multiplexed I/O & Peripheral Pin AD9 (General)
27	AD10	I/O	Multiplexed I/O & Peripheral Pin AD10 (General)
28	AD11	I/O	Multiplexed I/O & Peripheral Pin AD11 (General)
29	AD12	I/O	Multiplexed I/O & Peripheral Pin AD12 (General)
30	AD13	I/O	Multiplexed I/O & Peripheral Pin AD13 (General)
31	AD14	I/O	Multiplexed I/O & Peripheral Pin AD14 (General)
32	PSPCFG0	I/O	Multiplexed I/O & Peripheral Pin PSPCFG0 (General)
33	VSS	GND	Ground Reference Pin (VSS)
34	CS#/CS	I/O	Multiplexed I/O & Peripheral Pin CS#/CS (General)
35	WR	I/O	Multiplexed I/O & Peripheral Pin WR (General)
36	SI	I/O	Multiplexed I/O & Peripheral Pin SI (SPI)
37	SCK	I/O	Multiplexed I/O & Peripheral Pin SCK (SPI)
38	AD0	I/O	Multiplexed I/O & Peripheral Pin AD0 (General)
39	AD1	I/O	Multiplexed I/O & Peripheral Pin AD1 (General)
40	AD2	I/O	Multiplexed I/O & Peripheral Pin AD2 (General)
41	AD3	I/O	Multiplexed I/O & Peripheral Pin AD3 (General)
42	VSS	GND	Ground Reference Pin (VSS)
43	VCAP	I/O	Multiplexed I/O & Peripheral Pin VCAP (General)
44	VDD	Power	Power Supply Input (VDD — 3.0V to 3.6V)
45	EPAD	GND	Exposed Thermal & Ground Pad (EPAD)

PIN 1 PSPMode10

I/O

Multiplexed I/O & Peripheral Pin PSPMode10 (General)

Design note: Signal terminal PSPMode10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PSPMode10. Supported peripheral buses: General.

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 11 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

ENC424J600T-I/ML (QFN-44-EP(8x8)) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

ENC424J600T-I/ML (QFN-44-EP(8x8)) - 2. Standard Pinout (Top View)

True package pinout (45 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

ENC424J600T-I/ML (QFN-44-EP(8x8)) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

ENC424J600T-I/ML (QFN-44-EP(8x8)) - 4. Package Dimensions (D×E×A)

QFN-44-EP(8x8) · 8.00×8.00mm · Pitch 0.65mmExpand ›

5. Recommended Land PatternLAND PATTERN

ENC424J600T-I/ML (QFN-44-EP(8x8)) - 5. Recommended Land Pattern

IPC-7351B Footprint (45 Pads)Expand ›

6. Application SchematicSCHEMATIC

ENC424J600T-I/ML (QFN-44-EP(8x8)) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (11 figures · Page 1/1)

Showing 1–11 of 11 uncropped original figures for ENC424 / ENC624

P2 · p02_fig011777×1640px

ENC424J600T-I/ML (QFN-44-EP(8x8)) — DS39935C-page ii  2010 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology In

DS39935C-page ii  2010 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology In

P2 · p02_fig02786×285px

DS39935C-page ii  2010 Microchip Technology Inc.

P13 · p13_fig011777×1210px

FIGURE 2-5: TYPICAL ETHERNET MAGNETICS CONNECTIONS

P13 · p13_fig01P13

Datasheet Page 13 (p13_fig01)

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FIGURE 2-6: ALTERNATE TX CHOKE TOPOLOGY

P14 · p14_fig02867×352px

FIGURE 2-8: BI-COLOR LED CONNECTION

P15 · p15_fig011777×873px

FIGURE 2-9: USING THE INT/SPISEL PIN TO SELECT THE I/O INTERFACE

P151 · p151_fig02428×1530px

ENC424J600 | Example | -I/ML | 1010017 | Example | ENC424J600 -I/PT | 1010017 | Example | ENC624J600 -I/PT | 1010017 | 3 e | 3 e | 3 e

P151 · p151_fig031777×756px

ENC424J600T-I/ML (QFN-44-EP(8x8)) —  2010 Microchip Technology Inc. DS39935C-page 149 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spe

 2010 Microchip Technology Inc. DS39935C-page 149 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spe

P151 · p151_fig03P151

Datasheet Page 151 (p151_fig03)

P151 · p151_fig01All Packages in PDF

18.1 Package Marking Information

Technical Specifications & Part Details (ENC424J600T-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:ENC424J600T-I/ML (QFN-44-EP(8x8)) is a 44-pin standard electronic & interconnect component featuring a 8.00 × 8.00 × 0.90 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 3.0V to 3.6V supply operation across -40°C to +85°C with integrated SPI, RTC/CLK interfaces.

Operating Supply VoltageV_CC / V_DD

3.0V to 3.6V

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

-40°C to +85°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

25 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

8.00 × 8.00 × 0.90 mm (A1=0.03 mm)

Package family: QFN (QFN-44-EP(8x8))

Pin Count & Lead PitchN / e

44 Pins | Pitch e = 0.65 mm (25.6 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

SPI, RTC/CLK

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol45 auto-grouped pins

IPC-7351B Land Pattern45 pads · Pitch 0.65mm

IPC-7525 60% Solder PasteEPAD 6.55×6.55mm windowed grid

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

IPC-7351B

Family Variants & Same Datasheet Chips — ENC424 / ENC624 (2)

Select package variant or sibling MPN sharing this datasheet

QFN-44-EP(8x8) · 45P

ENC424J600T-I/ML

MICROCHIP·QFN-44-EP(8x8)

IPC-7351B

45P8.0×8.0×0.90mmP=0.65mm

ENC424 / ENC624 (QFN-44-EP(8x8))

TQFP-64(10x10) · 64P

ENC624J600-I/PT

MICROCHIP·TQFP-64(10x10)

IPC-7351B

64P10.0×10.0×1.20mmP=0.5mm

ENC424 / ENC624 (TQFP-64(10x10))

Mechanical Dimensions & Land Pattern (QFN-44-EP(8x8))

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

8.00 × 8.00 mm

Height (A) & Pitch (e)IPC-7351B

A=0.90mm · e=0.65mm

Pad Size (W × L)Level B

0.28 × 0.80 mm

Pins / Total PadsTopology

45P / 45Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit QFN-44-EP(8x8)	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ENC424J600T-I/ML (QFN-44-EP(8x8))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ENC424J600T-I/ML (QFN-44-EP(8x8))?

Manufactured by MICROCHIP, the ENC424J600T-I/ML is housed in a QFN-44-EP(8x8) package with 45 pins and a 0.65 mm lead pitch, supporting a VCC supply range of 3.0V to 3.6V. Key pins include: 1 (PSPMode10: Multiplexed I/O & Peripheral Pin PSPMode10 (General)), 2 (OSC2: Multiplexed I/O & Peripheral Pin OSC2 (RTC/CLK)), 3 (OSC1: Multiplexed I/O & Peripheral Pin OSC1 (RTC/CLK)), 4 (VDDOSC: Power Supply Input (VDDOSC — 3.0V to 3.6V)), 5 (AD4: Multiplexed I/O & Peripheral Pin AD4 (General)), 6 (AD5: Multiplexed I/O & Peripheral Pin AD5 (General)).

What are the IPC-7351B PCB Footprint dimensions for ENC424J600T-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ENC424J600T-I/ML (QFN-44-EP(8x8)) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.65 mm, and 45 copper pads plus a central exposed thermal pad (EPAD) of 6.55 × 6.55 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ENC424J600T-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ENC424J600T-I/ML (MICROCHIP, QFN-44-EP(8x8)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (45 pins) & ENC424 / ENC624 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	PSPMode10	Digital_IO	Signal terminal PSPMode10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PSPMode10. Supported peripheral buses: General.
2	OSC2	Digital_IO	Signal terminal OSC2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC2. Supported peripheral buses: RTC/CLK.
3	OSC1	Digital_IO	Signal terminal OSC1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: OSC1. Supported peripheral buses: RTC/CLK.
4	VDDOSC	Power_In	Primary positive power supply input (VDDOSC) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
5	AD4	Digital_IO	Signal terminal AD4 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD4. Supported peripheral buses: General.
6	AD5	Digital_IO	Signal terminal AD5 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD5. Supported peripheral buses: General.
7	AD6	Digital_IO	Signal terminal AD6 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD6. Supported peripheral buses: General.
8	AD7	Digital_IO	Signal terminal AD7 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD7. Supported peripheral buses: General.
9	LEDB	Digital_IO	Signal terminal LEDB (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: LEDB. Supported peripheral buses: General.
10	LEDA	Digital_IO	Signal terminal LEDA (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: LEDA. Supported peripheral buses: General.
11	RBIAS	Digital_IO	Signal terminal RBIAS (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: RBIAS. Supported peripheral buses: General.
12	VDDPLL	Power_In	Primary positive power supply input (VDDPLL) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
13	VSSPLL	GND	0V electrical ground return terminal (VSSPLL) for internal core logic, I/O drivers, and analog sub-blocks.
14	VSSRX	GND	0V electrical ground return terminal (VSSRX) for internal core logic, I/O drivers, and analog sub-blocks.
15	VDDRX	Power_In	Primary positive power supply input (VDDRX) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
16	TPIN+	Digital_IO	Signal terminal TPIN+ (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TPIN+. Supported peripheral buses: General.
17	TPIN -	Digital_IO	Signal terminal TPIN - (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TPIN -. Supported peripheral buses: General.
18	VDDTX	Power_In	Primary positive power supply input (VDDTX) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
19	VSSTX	GND	0V electrical ground return terminal (VSSTX) for internal core logic, I/O drivers, and analog sub-blocks.
20	TPOUT+	Digital_IO	Signal terminal TPOUT+ (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TPOUT+. Supported peripheral buses: General.
21	TPOUT -	Digital_IO	Signal terminal TPOUT - (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: TPOUT -. Supported peripheral buses: General.
22	VSSTX	GND	0V electrical ground return terminal (VSSTX) for internal core logic, I/O drivers, and analog sub-blocks.
23	CLKOUT	Digital_IO	Signal terminal CLKOUT (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: CLKOUT. Supported peripheral buses: General.
24	SPISEL	Digital_IO	Signal terminal SPISEL (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI.
25	AD8	Digital_IO	Signal terminal AD8 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD8. Supported peripheral buses: General.
26	AD9	Digital_IO	Signal terminal AD9 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD9. Supported peripheral buses: General.
27	AD10	Digital_IO	Signal terminal AD10 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD10. Supported peripheral buses: General.
28	AD11	Digital_IO	Signal terminal AD11 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD11. Supported peripheral buses: General.
29	AD12	Digital_IO	Signal terminal AD12 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD12. Supported peripheral buses: General.
30	AD13	Digital_IO	Signal terminal AD13 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD13. Supported peripheral buses: General.
31	AD14	Digital_IO	Signal terminal AD14 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD14. Supported peripheral buses: General.
32	PSPCFG0	Digital_IO	Signal terminal PSPCFG0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: PSPCFG0. Supported peripheral buses: General.
33	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
34	CS#/CS	Digital_IO	Signal terminal CS#/CS (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: CS#/CS. Supported peripheral buses: General.
35	WR	Digital_IO	Signal terminal WR (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: WR. Supported peripheral buses: General.
36	SI	Digital_IO	Signal terminal SI (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SPISERIALDATAINPUT. Supported peripheral buses: SPI.
37	SCK	Digital_IO	Signal terminal SCK (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: SPISERIALCLOCKINPUT. Supported peripheral buses: SPI.
38	AD0	Digital_IO	Signal terminal AD0 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD0. Supported peripheral buses: General.
39	AD1	Digital_IO	Signal terminal AD1 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD1. Supported peripheral buses: General.
40	AD2	Digital_IO	Signal terminal AD2 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD2. Supported peripheral buses: General.
41	AD3	Digital_IO	Signal terminal AD3 (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: AD3. Supported peripheral buses: General.
42	VSS	GND	0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
43	VCAP	Digital_IO	Signal terminal VCAP (I/O, 3.0V to 3.6V domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
44	VDD	Power_In	Primary positive power supply input (VDD) operating in the 3.0V to 3.6V domain (Max rating: 3.6V).
45	EPAD	GND	Bottom exposed die attach pad (EPAD) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.

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