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PIC16F628-04/SO (SOIC-18-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16F628-04/SO

MICROCHIPID: C184833SOIC-18-300mil · 18 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16F628-04/SO (SOIC-18-300mil)1RA2/AN2/VREF2RA3/AN3/CMP13RA4/TOCKI/CM4RA5/MCLR/VPP5VSS6RB0/INT7RB1/RX/DT8RB2/TX/CK9RB3/CCP118RA1/AN117RA0/AN016RA7/OSC1/CLK15RA6/OSC2/CLK14VDD13RB7/T1OSI/PG12RB6/T1OSO/T111RB510RB4/PGMGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
123456789101112131415161718E=7.50mm · Pitch e=1.27mmD=11.55mm-8-6-4-20246897531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 7.50mm × 11.55mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (18/18)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RA2/AN2/VREFAnalogMultiplexed I/O & Peripheral Pin RA2/AN2/VREF (General)
2RA3/AN3/CMP1I/OMultiplexed I/O & Peripheral Pin RA3/AN3/CMP1 (General)
3RA4/TOCKI/CMP2I/OMultiplexed I/O & Peripheral Pin RA4/TOCKI/CMP2 (General)
4RA5/MCLR/VPPI/OMultiplexed I/O & Peripheral Pin RA5/MCLR/VPP (General)
5VSSGNDGround Reference Pin (VSS)
6RB0/INTI/OMultiplexed I/O & Peripheral Pin RB0/INT (General)
7RB1/RX/DTI/OMultiplexed I/O & Peripheral Pin RB1/RX/DT (General)
8RB2/TX/CKI/OMultiplexed I/O & Peripheral Pin RB2/TX/CK (General)
9RB3/CCP1I/OMultiplexed I/O & Peripheral Pin RB3/CCP1 (General)
10RB4/PGMI/OMultiplexed I/O & Peripheral Pin RB4/PGM (General)
11RB5I/OMultiplexed I/O & Peripheral Pin RB5 (General)
12RB6/T1OSO/T1CKI/PGCI/OMultiplexed I/O & Peripheral Pin RB6/T1OSO/T1CKI/PGC (General)
13RB7/T1OSI/PGDI/OMultiplexed I/O & Peripheral Pin RB7/T1OSI/PGD (General)
14VDDPowerPower Supply Input (VDD — 3.0V to 5.5V)
15RA6/OSC2/CLKOUTI/OMultiplexed I/O & Peripheral Pin RA6/OSC2/CLKOUT (RTC/CLK)
16RA7/OSC1/CLKINI/OMultiplexed I/O & Peripheral Pin RA7/OSC1/CLKIN (RTC/CLK)
17RA0/AN0I/OMultiplexed I/O & Peripheral Pin RA0/AN0 (General)
18RA1/AN1I/OMultiplexed I/O & Peripheral Pin RA1/AN1 (General)
PIN 1 RA2/AN2/VREF
Analog
Multiplexed I/O & Peripheral Pin RA2/AN2/VREF (General)
Design note: RA2
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC16F628-04/SO (MICROCHIP · SOIC-18-300mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC16F628-04/SO (SOIC-18-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16F628-04/SO (SOIC-18-300mil) - 2. Standard Pinout (Top View)
True package pinout (18 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16F628-04/SO (SOIC-18-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16F628-04/SO (SOIC-18-300mil) - 4. Package Dimensions (D×E×A)
SOIC-18-300mil · 7.50×11.55mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16F628-04/SO (SOIC-18-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (18 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16F628-04/SO (SOIC-18-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for PIC16F628
P159 · p159_fig01EXACT PACKAGE
PIC16F628-04/SO (SOIC-18-300mil) — 19.1 Package Marking Information
19.1 Package Marking Information
P2 · p02_fig011782×2485px
PIC16F628-04/SO (SOIC-18-300mil) — DS40300C - page ii Preliminary  2003 Microchip Technology Inc. | Trademarks | The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporat
DS40300C - page ii Preliminary  2003 Microchip Technology Inc. | Trademarks | The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART and PRO MATE are registered trademarks of Microchip Technology Incorporat
P2 · p02_fig02672×376px
PIC16F628-04/SO (SOIC-18-300mil) — DS40300C - page ii Preliminary  2003 Microchip Technology Inc.
DS40300C - page ii Preliminary  2003 Microchip Technology Inc.
P2 · p02_fig02P2
PIC16F628-04/SO (SOIC-18-300mil) — Datasheet Page 2 (p02_fig02)
Datasheet Page 2 (p02_fig02)
P64 · p64_fig01871×671px
PIC16F628-04/SO (SOIC-18-300mil) — match RB3/CCP1
match RB3/CCP1
P64 · p64_fig02868×647px
PIC16F628-04/SO (SOIC-18-300mil) — FIGURE 11-1: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>)
FIGURE 11-1: COMPARE MODE OPERATION BLOCK DIAGRAM Special Event Trigger will reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>)
P108 · p108_fig01870×413px
PIC16F628-04/SO (SOIC-18-300mil) — FIGURE 14-18: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
FIGURE 14-18: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
P108 · p108_fig02868×859px
PIC16F628-04/SO (SOIC-18-300mil) — FIGURE 14-18: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
FIGURE 14-18: TYPICAL IN-CIRCUIT SERIAL PROGRAMMING CONNECTION
P108 · p108_fig02P108
PIC16F628-04/SO (SOIC-18-300mil) — Datasheet Page 108 (p108_fig02)
Datasheet Page 108 (p108_fig02)
P109 · p109_fig01733×950px
PIC16F628-04/SO (SOIC-18-300mil) — FIGURE 15-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0
FIGURE 15-1: GENERAL FORMAT FOR INSTRUCTIONS Byte-oriented file register operations 13 8 7 6 0
P159 · p159_fig01P159
PIC16F628-04/SO (SOIC-18-300mil) — Datasheet Page 159 (p159_fig01)
Datasheet Page 159 (p159_fig01)
P160 · p160_fig011443×1806px
PIC16F628-04/SO (SOIC-18-300mil) — 15 10 5 15 10 5 β Mold Draft Angle Bottom | 15 10 5 15 10 5 α Mold Draft Angle Top | 10.92 9.40 7.87 .430 .370 .310 eB Overall Row Spacing § | 0.56 0.46 0.36 .022 .018 .014 B Lower Lead Width | 1.78 1.46 1.14 .070 .058 .045 B1 Upper Lead Wi
15 10 5 15 10 5 β Mold Draft Angle Bottom | 15 10 5 15 10 5 α Mold Draft Angle Top | 10.92 9.40 7.87 .430 .370 .310 eB Overall Row Spacing § | 0.56 0.46 0.36 .022 .018 .014 B Lower Lead Width | 1.78 1.46 1.14 .070 .058 .045 B1 Upper Lead Wi
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (PIC16F628-04/SO)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16F628-04/SO (SOIC-18-300mil) is a 18-pin standard electronic & interconnect component featuring a 11.55 × 7.50 × 2.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 3.0V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
11.55 × 7.50 × 2.70 mm (A1=0.20 mm)
Package family: SOIC (SOIC-18-300mil)
Pin Count & Lead PitchN / e
18 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol18 auto-grouped pins
OK
IPC-7351B Land Pattern18 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-18-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
11.55 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.70mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
18P / 18Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-18-300mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16F628-04/SO (SOIC-18-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16F628-04/SO (SOIC-18-300mil)?

Manufactured by MICROCHIP, the PIC16F628-04/SO is housed in a SOIC-18-300mil package with 18 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3.0V to 5.5V. Key pins include: 1 (RA2/AN2/VREF: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF (General)), 2 (RA3/AN3/CMP1: Multiplexed I/O & Peripheral Pin RA3/AN3/CMP1 (General)), 3 (RA4/TOCKI/CMP2: Multiplexed I/O & Peripheral Pin RA4/TOCKI/CMP2 (General)), 4 (RA5/MCLR/VPP: Multiplexed I/O & Peripheral Pin RA5/MCLR/VPP (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RB0/INT: Multiplexed I/O & Peripheral Pin RB0/INT (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16F628-04/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16F628-04/SO (SOIC-18-300mil) has a nominal body envelope of 7.50 × 11.55 mm, pitch e = 1.27 mm, and 18 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16F628-04/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16F628-04/SO (MICROCHIP, SOIC-18-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (18 pins) & PIC16F628 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RA2/AN2/VREFAnalogSignal terminal RA2/AN2/VREF (Analog, 3.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF. Supported peripheral buses: General.
2RA3/AN3/CMP1Digital_IOSignal terminal RA3/AN3/CMP1 (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/CMP1. Supported peripheral buses: General.
3RA4/TOCKI/CMP2Digital_IOSignal terminal RA4/TOCKI/CMP2 (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RA4/TOCKI/CMP2. Supported peripheral buses: General.
4RA5/MCLR/VPPDigital_IOSignal terminal RA5/MCLR/VPP (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RA5/MCLR/VPP. Supported peripheral buses: General.
5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6RB0/INTDigital_IOSignal terminal RB0/INT (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RB0/INT. Supported peripheral buses: General.
7RB1/RX/DTDigital_IOSignal terminal RB1/RX/DT (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RB1/RX/DT. Supported peripheral buses: General.
8RB2/TX/CKDigital_IOSignal terminal RB2/TX/CK (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RB2/TX/CK. Supported peripheral buses: General.
9RB3/CCP1Digital_IOSignal terminal RB3/CCP1 (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RB3/CCP1. Supported peripheral buses: General.
10RB4/PGMDigital_IOSignal terminal RB4/PGM (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RB4/PGM. Supported peripheral buses: General.
11RB5Digital_IOSignal terminal RB5 (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
12RB6/T1OSO/T1CKI/PGCDigital_IOSignal terminal RB6/T1OSO/T1CKI/PGC (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RB6/T1OSO/T1CKI/PGC. Supported peripheral buses: General.
13RB7/T1OSI/PGDDigital_IOSignal terminal RB7/T1OSI/PGD (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RB7/T1OSI/PGD. Supported peripheral buses: General.
14VDDPower_InPrimary positive power supply input (VDD) operating in the 3.0V to 5.5V domain (Max rating: 5.5V).
15RA6/OSC2/CLKOUTDigital_IOSignal terminal RA6/OSC2/CLKOUT (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RA6/OSC2/CLKOUT. Supported peripheral buses: RTC/CLK.
16RA7/OSC1/CLKINDigital_IOSignal terminal RA7/OSC1/CLKIN (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RA7/OSC1/CLKIN. Supported peripheral buses: RTC/CLK.
17RA0/AN0Digital_IOSignal terminal RA0/AN0 (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
18RA1/AN1Digital_IOSignal terminal RA1/AN1 (I/O, 3.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
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