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LAN8187I-JT (TQFP-64(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

LAN8187I-JT

MICROCHIPID: C184729TQFP-64(10x10) · 64 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · LAN8187I-JT (TQFP-64(10x10))1GPO0/RMII2GPO1/PHYAD43GPO24MODE05MODE16MODE27VSS18NC9VSS710VSS811NC12NC13VDD3314VDD_CORE15VSS216SPEED100/PHY17LINK/PHYAD118NC19ACTIVITY/PHY20FDUPLEX/PHYA21NC22XTAL223CLKIN/XTAL124VSS325nRST26MDIO27MDC28VSS429RXD3/nINTSEL30RXD231RXD132RXD064NC63REG_EN62VSS661AVDD360AVSS459EXRES158AVSS357AVDD256NC55RXP54RXN53AVDD152AVSS251TXP50TXN49AVSS148CRS47COL/CRS_DV46nINT/TX_ER/T45TXD344TXD243VDDIO42TXD141TXD040VSS539TX_EN38TX_CLK37AMDIX_EN36CH_SELECT35RX_ER/RXD434RX_CLK33RX_DVGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GPO0/RMIII/OMultiplexed I/O & Peripheral Pin GPO0/RMII (General)
2GPO1/PHYAD4I/OMultiplexed I/O & Peripheral Pin GPO1/PHYAD4 (General)
3GPO2I/OMultiplexed I/O & Peripheral Pin GPO2 (General)
4MODE0I/OMultiplexed I/O & Peripheral Pin MODE0 (General)
5MODE1I/OMultiplexed I/O & Peripheral Pin MODE1 (General)
6MODE2I/OMultiplexed I/O & Peripheral Pin MODE2 (General)
7VSS1GNDGround Reference Pin (VSS1)
8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
9VSS7GNDGround Reference Pin (VSS7)
10VSS8GNDGround Reference Pin (VSS8)
11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
12NCI/OMultiplexed I/O & Peripheral Pin NC (General)
13VDD33PowerPower Supply Input (VDD33 — 3.3V to 1.8V)
14VDD_COREPowerPower Supply Input (VDD_CORE — 3.3V to 1.8V)
15VSS2GNDGround Reference Pin (VSS2)
16SPEED100/PHYAD0I/OMultiplexed I/O & Peripheral Pin SPEED100/PHYAD0 (General)
17LINK/PHYAD1I/OMultiplexed I/O & Peripheral Pin LINK/PHYAD1 (General)
18NCI/OMultiplexed I/O & Peripheral Pin NC (General)
19ACTIVITY/PHYAD2I/OMultiplexed I/O & Peripheral Pin ACTIVITY/PHYAD2 (General)
20FDUPLEX/PHYAD3I/OMultiplexed I/O & Peripheral Pin FDUPLEX/PHYAD3 (General)
21NCI/OMultiplexed I/O & Peripheral Pin NC (General)
22XTAL2I/OMultiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)
23CLKIN/XTAL1I/OMultiplexed I/O & Peripheral Pin CLKIN/XTAL1 (RTC/CLK)
24VSS3GNDGround Reference Pin (VSS3)
25nRSTISystem Enable & Hardware Reset (nRST)
26MDIOI/OMultiplexed I/O & Peripheral Pin MDIO (General)
27MDCI/OMultiplexed I/O & Peripheral Pin MDC (General)
28VSS4GNDGround Reference Pin (VSS4)
29RXD3/nINTSELI/OMultiplexed I/O & Peripheral Pin RXD3/nINTSEL (UART)
30RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
31RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
32RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
33RX_DVI/OMultiplexed I/O & Peripheral Pin RX_DV (General)
34RX_CLKI/OMultiplexed I/O & Peripheral Pin RX_CLK (General)
35RX_ER/RXD4I/OMultiplexed I/O & Peripheral Pin RX_ER/RXD4 (UART)
36CH_SELECTI/OMultiplexed I/O & Peripheral Pin CH_SELECT (General)
37AMDIX_ENI/OMultiplexed I/O & Peripheral Pin AMDIX_EN (General)
38TX_CLKI/OMultiplexed I/O & Peripheral Pin TX_CLK (General)
39TX_ENI/OMultiplexed I/O & Peripheral Pin TX_EN (General)
40VSS5GNDGround Reference Pin (VSS5)
41TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
42TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
43VDDIOPowerPower Supply Input (VDDIO — 3.3V to 1.8V)
44TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
45TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
46nINT/TX_ER/TXD4I/OMultiplexed I/O & Peripheral Pin nINT/TX_ER/TXD4 (UART)
47COL/CRS_DVI/OMultiplexed I/O & Peripheral Pin COL/CRS_DV (General)
48CRSI/OMultiplexed I/O & Peripheral Pin CRS (General)
49AVSS1GNDExposed Thermal & Ground Pad (AVSS1)
50TXNI/OMultiplexed I/O & Peripheral Pin TXN (General)
51TXPI/OMultiplexed I/O & Peripheral Pin TXP (General)
52AVSS2GNDGround Reference Pin (AVSS2)
53AVDD1PowerPower Supply Input (AVDD1 — 3.3V to 1.8V)
54RXNI/OMultiplexed I/O & Peripheral Pin RXN (General)
55RXPI/OMultiplexed I/O & Peripheral Pin RXP (General)
56NCI/OMultiplexed I/O & Peripheral Pin NC (General)
57AVDD2PowerPower Supply Input (AVDD2 — 3.3V to 1.8V)
58AVSS3GNDGround Reference Pin (AVSS3)
59EXRES1I/OMultiplexed I/O & Peripheral Pin EXRES1 (General)
60AVSS4GNDGround Reference Pin (AVSS4)
61AVDD3PowerPower Supply Input (AVDD3 — 3.3V to 1.8V)
62VSS6GNDGround Reference Pin (VSS6)
63REG_ENI/OMultiplexed I/O & Peripheral Pin REG_EN (General)
64NCI/OMultiplexed I/O & Peripheral Pin NC (General)
PIN 1 GPO0/RMII
I/O
Multiplexed I/O & Peripheral Pin GPO0/RMII (General)
Design note: Signal terminal GPO0/RMII (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: GPO0/RMII. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 6 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: LAN8187I-JT (MICROCHIP · TQFP-64(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
LAN8187I-JT (TQFP-64(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
LAN8187I-JT (TQFP-64(10x10)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
LAN8187I-JT (TQFP-64(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LAN8187I-JT (TQFP-64(10x10)) - 4. Package Dimensions (D×E×A)
TQFP-64(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
LAN8187I-JT (TQFP-64(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
LAN8187I-JT (TQFP-64(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (6 figures · Page 1/1)
Showing 1–6 of 6 uncropped original figures for LAN8187
P67 · p67_fig01EXACT PACKAGE
LAN8187I-JT (TQFP-64(10x10)) — FIGURE 9-1: 64-PIN TQFP PACKAGE OUTLINE, 10X10X1.4 BODY, 12X12MM FOOTPRINT
FIGURE 9-1: 64-PIN TQFP PACKAGE OUTLINE, 10X10X1.4 BODY, 12X12MM FOOTPRINT
P1 · p01_fig01377×200px
LAN8187I-JT (TQFP-64(10x10)) — MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX
MII/RMII 10/100 Ethernet Transceiver with HP Auto-MDIX
P6 · p06_fig011782×2094px
LAN8187I-JT (TQFP-64(10x10)) — FIGURE 2-1: PACKAGE PINOUT (TOP VIEW)
FIGURE 2-1: PACKAGE PINOUT (TOP VIEW)
P6 · p06_fig01P6
LAN8187I-JT (TQFP-64(10x10)) — Datasheet Page 6 (p06_fig01)
Datasheet Page 6 (p06_fig01)
P67 · p67_fig02202×433px
LAN8187I-JT (TQFP-64(10x10)) — PDF Figure p67_fig02 (Page 67 — PACKAGE_DIMENSIONS)
PDF Figure p67_fig02 (Page 67 — PACKAGE_DIMENSIONS)
P67 · p67_fig01P67
LAN8187I-JT (TQFP-64(10x10)) — Datasheet Page 67 (p67_fig01)
Datasheet Page 67 (p67_fig01)

Technical Specifications & Part Details (LAN8187I-JT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:LAN8187I-JT (TQFP-64(10x10)) is a 64-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.20 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.3V to 1.8V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 1.8V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.20 mm (A1=0.10 mm)
Package family: TQFP (TQFP-64(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 1.25 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-64(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — LAN8187I-JT (TQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of LAN8187I-JT (TQFP-64(10x10))?

Manufactured by MICROCHIP, the LAN8187I-JT is housed in a TQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 3.3V to 1.8V. Key pins include: 1 (GPO0/RMII: Multiplexed I/O & Peripheral Pin GPO0/RMII (General)), 2 (GPO1/PHYAD4: Multiplexed I/O & Peripheral Pin GPO1/PHYAD4 (General)), 3 (GPO2: Multiplexed I/O & Peripheral Pin GPO2 (General)), 4 (MODE0: Multiplexed I/O & Peripheral Pin MODE0 (General)), 5 (MODE1: Multiplexed I/O & Peripheral Pin MODE1 (General)), 6 (MODE2: Multiplexed I/O & Peripheral Pin MODE2 (General)).

What are the IPC-7351B PCB Footprint dimensions for LAN8187I-JT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), LAN8187I-JT (TQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for LAN8187I-JT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for LAN8187I-JT (MICROCHIP, TQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & LAN8187 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GPO0/RMIIDigital_IOSignal terminal GPO0/RMII (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: GPO0/RMII. Supported peripheral buses: General.
2GPO1/PHYAD4Digital_IOSignal terminal GPO1/PHYAD4 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: GPO1/PHYAD4. Supported peripheral buses: General.
3GPO2Digital_IOSignal terminal GPO2 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: GPO2. Supported peripheral buses: General.
4MODE0Digital_IOSignal terminal MODE0 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: MODE0. Supported peripheral buses: General.
5MODE1Digital_IOSignal terminal MODE1 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: MODE1. Supported peripheral buses: General.
6MODE2Digital_IOSignal terminal MODE2 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: MODE2. Supported peripheral buses: General.
7VSS1GND0V electrical ground return terminal (VSS1) for internal core logic, I/O drivers, and analog sub-blocks.
8NCNCSignal terminal NC (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
9VSS7GND0V electrical ground return terminal (VSS7) for internal core logic, I/O drivers, and analog sub-blocks.
10VSS8GND0V electrical ground return terminal (VSS8) for internal core logic, I/O drivers, and analog sub-blocks.
11NCNCSignal terminal NC (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
12NCNCSignal terminal NC (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
13VDD33Power_InPrimary positive power supply input (VDD33) operating in the 3.3V to 1.8V domain (Max rating: 3.3V).
14VDD_COREPower_InPrimary positive power supply input (VDD_CORE) operating in the 3.3V to 1.8V domain (Max rating: 3.3V).
15VSS2GND0V electrical ground return terminal (VSS2) for internal core logic, I/O drivers, and analog sub-blocks.
16SPEED100/PHYAD0Digital_IOSignal terminal SPEED100/PHYAD0 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: SPEED100/PHYAD0. Supported peripheral buses: General.
17LINK/PHYAD1Digital_IOSignal terminal LINK/PHYAD1 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: LINK/PHYAD1. Supported peripheral buses: General.
18NCNCSignal terminal NC (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
19ACTIVITY/PHYAD2Digital_IOSignal terminal ACTIVITY/PHYAD2 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: ACTIVITY/PHYAD2. Supported peripheral buses: General.
20FDUPLEX/PHYAD3Digital_IOSignal terminal FDUPLEX/PHYAD3 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: FDUPLEX/PHYAD3. Supported peripheral buses: General.
21NCNCSignal terminal NC (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
22XTAL2Digital_IOSignal terminal XTAL2 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK.
23CLKIN/XTAL1Digital_IOSignal terminal CLKIN/XTAL1 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: CLKIN/XTAL1. Supported peripheral buses: RTC/CLK.
24VSS3GND0V electrical ground return terminal (VSS3) for internal core logic, I/O drivers, and analog sub-blocks.
25nRSTDigital_IOActive-low hardware reset terminal (nRST): pulling this pin Low resets the processor core and peripherals.
26MDIODigital_IOSignal terminal MDIO (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: MDIO. Supported peripheral buses: General.
27MDCDigital_IOSignal terminal MDC (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: MDC. Supported peripheral buses: General.
28VSS4GND0V electrical ground return terminal (VSS4) for internal core logic, I/O drivers, and analog sub-blocks.
29RXD3/nINTSELDigital_IOSignal terminal RXD3/nINTSEL (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: RXD3/nINTSEL. Supported peripheral buses: UART.
30RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
31RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
32RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
33RX_DVDigital_IOSignal terminal RX_DV (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: RX_DV. Supported peripheral buses: General.
34RX_CLKDigital_IOSignal terminal RX_CLK (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: RX_CLK. Supported peripheral buses: General.
35RX_ER/RXD4Digital_IOSignal terminal RX_ER/RXD4 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: RX_ER/RXD4. Supported peripheral buses: UART.
36CH_SELECTDigital_IOSignal terminal CH_SELECT (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: CH_SELECT. Supported peripheral buses: General.
37AMDIX_ENDigital_IOSignal terminal AMDIX_EN (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: AMDIX_EN. Supported peripheral buses: General.
38TX_CLKDigital_IOSignal terminal TX_CLK (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: TX_CLK. Supported peripheral buses: General.
39TX_ENDigital_IOSignal terminal TX_EN (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: TX_EN. Supported peripheral buses: General.
40VSS5GND0V electrical ground return terminal (VSS5) for internal core logic, I/O drivers, and analog sub-blocks.
41TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
42TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
43VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V to 1.8V domain (Max rating: 3.3V).
44TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
45TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
46nINT/TX_ER/TXD4Digital_IOSignal terminal nINT/TX_ER/TXD4 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: nINT/TX_ER/TXD4. Supported peripheral buses: UART.
47COL/CRS_DVDigital_IOSignal terminal COL/CRS_DV (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: COL/CRS_DV. Supported peripheral buses: General.
48CRSDigital_IOSignal terminal CRS (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: CRS. Supported peripheral buses: General.
49AVSS1GNDBottom exposed die attach pad (AVSS1) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
50TXNDigital_IOSignal terminal TXN (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: TXN. Supported peripheral buses: General.
51TXPDigital_IOSignal terminal TXP (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: TXP. Supported peripheral buses: General.
52AVSS2GND0V electrical ground return terminal (AVSS2) for internal core logic, I/O drivers, and analog sub-blocks.
53AVDD1Power_InPrimary positive power supply input (AVDD1) operating in the 3.3V to 1.8V domain (Max rating: 3.3V).
54RXNDigital_IOSignal terminal RXN (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: RXN. Supported peripheral buses: General.
55RXPDigital_IOSignal terminal RXP (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: RXP. Supported peripheral buses: General.
56NCNCSignal terminal NC (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
57AVDD2Power_InPrimary positive power supply input (AVDD2) operating in the 3.3V to 1.8V domain (Max rating: 3.3V).
58AVSS3GND0V electrical ground return terminal (AVSS3) for internal core logic, I/O drivers, and analog sub-blocks.
59EXRES1Digital_IOSignal terminal EXRES1 (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: EXRES1. Supported peripheral buses: General.
60AVSS4GND0V electrical ground return terminal (AVSS4) for internal core logic, I/O drivers, and analog sub-blocks.
61AVDD3Power_InPrimary positive power supply input (AVDD3) operating in the 3.3V to 1.8V domain (Max rating: 3.3V).
62VSS6GND0V electrical ground return terminal (VSS6) for internal core logic, I/O drivers, and analog sub-blocks.
63REG_ENDigital_IOSignal terminal REG_EN (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: REG_EN. Supported peripheral buses: General.
64NCNCSignal terminal NC (I/O, 3.3V to 1.8V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
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