ChipDocs.org
⌘K
2284 PARTSUpload PDF
PIC18F2221-E/SO (SOIC-28-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC18F2221-E/SO

MICROCHIPID: C184697SOIC-28-300mil · 28 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC18F2221-E/SO (SOIC-28-300mil)1MCLR#/VPP/RE2RA0/AN03RA1/AN14RA2/AN2/VREF5RA3/AN3/VREF6RA4/T0CKI/C17NC8VSS9OSC1/CLKI/RA10OSC2/CLKO/RA11RC0/T1OSO/T112RC1/T1OSI/CC13RC2/CCP114RC3/SCK/SCL28RB7/KBI3/PGD27RB6/KBI2/PGC26RB5/KBI1/PGM25RB4/KBI0/AN124RB3/AN9/CCP223RB2/INT2/AN822RB1/INT1/AN121RB0/INT0/FLT20VDD19VSS18RC7/RX/DT17RC6/TX/CK16RC5/SDO15RC4/SDI/SDAGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.822.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728E=7.50mm · Pitch e=1.27mmD=17.90mm-10-8-6-4-20246810131197531-1-3-5-7-9-11-13mm
3. 3D CAD MODEL
Package Body: 7.50mm × 17.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (28/28)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1MCLR#/VPP/RE3I/OMultiplexed I/O & Peripheral Pin MCLR#/VPP/RE3 (General)
2RA0/AN0I/OMultiplexed I/O & Peripheral Pin RA0/AN0 (General)
3RA1/AN1I/OMultiplexed I/O & Peripheral Pin RA1/AN1 (General)
4RA2/AN2/VREF-/CVREFAnalogMultiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)
5RA3/AN3/VREF+AnalogMultiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)
6RA4/T0CKI/C1OUTI/OMultiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)
7NCNCNo Connect (Leave Floating)
8VSSGNDGround Reference Pin (VSS)
9OSC1/CLKI/RA7I/OMultiplexed I/O & Peripheral Pin OSC1/CLKI/RA7 (RTC/CLK)
10OSC2/CLKO/RA6I/OMultiplexed I/O & Peripheral Pin OSC2/CLKO/RA6 (RTC/CLK)
11RC0/T1OSO/T13CKII/OMultiplexed I/O & Peripheral Pin RC0/T1OSO/T13CKI (General)
12RC1/T1OSI/CCP2I/OMultiplexed I/O & Peripheral Pin RC1/T1OSI/CCP2 (General)
13RC2/CCP1I/OMultiplexed I/O & Peripheral Pin RC2/CCP1 (General)
14RC3/SCK/SCLI/OMultiplexed I/O & Peripheral Pin RC3/SCK/SCL (SPI, I2C)
15RC4/SDI/SDAI/OMultiplexed I/O & Peripheral Pin RC4/SDI/SDA (I2C)
16RC5/SDOI/OMultiplexed I/O & Peripheral Pin RC5/SDO (General)
17RC6/TX/CKI/OMultiplexed I/O & Peripheral Pin RC6/TX/CK (General)
18RC7/RX/DTI/OMultiplexed I/O & Peripheral Pin RC7/RX/DT (General)
19VSSGNDGround Reference Pin (VSS)
20VDDPowerPower Supply Input (VDD — 2.0V to 5.5V)
21RB0/INT0/FLT0/AN12I/OMultiplexed I/O & Peripheral Pin RB0/INT0/FLT0/AN12 (General)
22RB1/INT1/AN10I/OMultiplexed I/O & Peripheral Pin RB1/INT1/AN10 (General)
23RB2/INT2/AN8I/OMultiplexed I/O & Peripheral Pin RB2/INT2/AN8 (General)
24RB3/AN9/CCP2I/OMultiplexed I/O & Peripheral Pin RB3/AN9/CCP2 (General)
25RB4/KBI0/AN11I/OMultiplexed I/O & Peripheral Pin RB4/KBI0/AN11 (General)
26RB5/KBI1/PGMI/OMultiplexed I/O & Peripheral Pin RB5/KBI1/PGM (General)
27RB6/KBI2/PGCI/OMultiplexed I/O & Peripheral Pin RB6/KBI2/PGC (General)
28RB7/KBI3/PGDI/OMultiplexed I/O & Peripheral Pin RB7/KBI3/PGD (General)
PIN 1 MCLR#/VPP/RE3
I/O
Multiplexed I/O & Peripheral Pin MCLR#/VPP/RE3 (General)
Design note: Signal terminal MCLR#/VPP/RE3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR#/VPP/RE3. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: PIC18F2221-E/SO (MICROCHIP · SOIC-28-300mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
PIC18F2221-E/SO (SOIC-28-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC18F2221-E/SO (SOIC-28-300mil) - 2. Standard Pinout (Top View)
True package pinout (28 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC18F2221-E/SO (SOIC-28-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC18F2221-E/SO (SOIC-28-300mil) - 4. Package Dimensions (D×E×A)
SOIC-28-300mil · 7.50×17.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC18F2221-E/SO (SOIC-28-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (28 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC18F2221-E/SO (SOIC-28-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for PIC18F2221
P2 · p02_fig011777×1640px
PIC18F2221-E/SO (SOIC-28-300mil) — DS39689F-page 2 © 2009 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Inc
DS39689F-page 2 © 2009 Microchip Technology Inc. | Trademarks | FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Inc
P2 · p02_fig02788×285px
PIC18F2221-E/SO (SOIC-28-300mil) — DS39689F-page 2 © 2009 Microchip Technology Inc.
DS39689F-page 2 © 2009 Microchip Technology Inc.
P26 · p26_fig01867×940px
PIC18F2221-E/SO (SOIC-28-300mil) — FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS
FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS
P26 · p26_fig01P26
PIC18F2221-E/SO (SOIC-28-300mil) — Datasheet Page 26 (p26_fig01)
Datasheet Page 26 (p26_fig01)
P147 · p147_fig011777×345px
PIC18F2221-E/SO (SOIC-28-300mil) — FIGURE 16-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 16-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P147 · p147_fig021777×1051px
PIC18F2221-E/SO (SOIC-28-300mil) — FIGURE 16-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
FIGURE 16-1: CAPTURE MODE OPERATION BLOCK DIAGRAM
P148 · p148_fig011537×941px
PIC18F2221-E/SO (SOIC-28-300mil) — FIGURE 16-2: COMPARE MODE OPERATION BLOCK DIAGRAM
FIGURE 16-2: COMPARE MODE OPERATION BLOCK DIAGRAM
P171 · p171_fig011777×937px
PIC18F2221-E/SO (SOIC-28-300mil) — FIGURE 18-2: SPI MASTER/SLAVE CONNECTION
FIGURE 18-2: SPI MASTER/SLAVE CONNECTION
P174 · p174_fig011756×1059px
PIC18F2221-E/SO (SOIC-28-300mil) — FIGURE 18-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 0) Write to SSPBUF
FIGURE 18-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 0) Write to SSPBUF
P174 · p174_fig021777×1096px
PIC18F2221-E/SO (SOIC-28-300mil) — FIGURE 18-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 1) Write to SSPBUF
FIGURE 18-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) SS SCK (CKP = 0 SCK (CKP = 1 CKE = 1) Write to SSPBUF
P373 · p373_fig011777×2564px
PIC18F2221-E/SO (SOIC-28-300mil) — PIC18F2221/2321/4221/4321 FAMILY
PIC18F2221/2321/4221/4321 FAMILY
P376 · p376_fig011778×2637px
PIC18F2221-E/SO (SOIC-28-300mil) — PIC18F2221/2321/4221/4321 FAMILY - 28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] - hhttp://www.microchip.com/packaging | PIC18F2221/2321/4221/4321 FAMILY | DS39689F-page 376 © 2009 Microchip Technology Inc. | dêÜè nóܧ•î
PIC18F2221/2321/4221/4321 FAMILY - 28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] - hhttp://www.microchip.com/packaging | PIC18F2221/2321/4221/4321 FAMILY | DS39689F-page 376 © 2009 Microchip Technology Inc. | dêÜè nóܧ•î
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (PIC18F2221-E/SO)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC18F2221-E/SO (SOIC-28-300mil) is a 28-pin standard electronic & interconnect component featuring a 17.90 × 7.50 × 2.70 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 2.0V to 5.5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
17.90 × 7.50 × 2.70 mm (A1=0.20 mm)
Package family: SOIC (SOIC-28-300mil)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol28 auto-grouped pins
OK
IPC-7351B Land Pattern28 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-28-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
17.90 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.70mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
28P / 28Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-28-300mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC18F2221-E/SO (SOIC-28-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC18F2221-E/SO (SOIC-28-300mil)?

Manufactured by MICROCHIP, the PIC18F2221-E/SO is housed in a SOIC-28-300mil package with 28 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 2.0V to 5.5V. Key pins include: 1 (MCLR#/VPP/RE3: Multiplexed I/O & Peripheral Pin MCLR#/VPP/RE3 (General)), 2 (RA0/AN0: Multiplexed I/O & Peripheral Pin RA0/AN0 (General)), 3 (RA1/AN1: Multiplexed I/O & Peripheral Pin RA1/AN1 (General)), 4 (RA2/AN2/VREF-/CVREF: Multiplexed I/O & Peripheral Pin RA2/AN2/VREF-/CVREF (General)), 5 (RA3/AN3/VREF+: Multiplexed I/O & Peripheral Pin RA3/AN3/VREF+ (General)), 6 (RA4/T0CKI/C1OUT: Multiplexed I/O & Peripheral Pin RA4/T0CKI/C1OUT (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC18F2221-E/SO?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC18F2221-E/SO (SOIC-28-300mil) has a nominal body envelope of 7.50 × 17.90 mm, pitch e = 1.27 mm, and 28 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC18F2221-E/SO?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC18F2221-E/SO (MICROCHIP, SOIC-28-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (28 pins) & PIC18F2221 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1MCLR#/VPP/RE3Digital_IOSignal terminal MCLR#/VPP/RE3 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: MCLR#/VPP/RE3. Supported peripheral buses: General.
2RA0/AN0Digital_IOSignal terminal RA0/AN0 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA0/AN0. Supported peripheral buses: General.
3RA1/AN1Digital_IOSignal terminal RA1/AN1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA1/AN1. Supported peripheral buses: General.
4RA2/AN2/VREF-/CVREFAnalogSignal terminal RA2/AN2/VREF-/CVREF (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA2/AN2/VREF-/CVREF. Supported peripheral buses: General.
5RA3/AN3/VREF+AnalogSignal terminal RA3/AN3/VREF+ (Analog, 2.0V to 5.5V domain). Multiplexed alternate functions: RA3/AN3/VREF+. Supported peripheral buses: General.
6RA4/T0CKI/C1OUTDigital_IOSignal terminal RA4/T0CKI/C1OUT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RA4/T0CKI/C1OUT. Supported peripheral buses: General.
7NCNo_ConnectNo Connect (Leave Floating)
8VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
9OSC1/CLKI/RA7Digital_IOSignal terminal OSC1/CLKI/RA7 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC1/CLKI/RA7. Supported peripheral buses: RTC/CLK.
10OSC2/CLKO/RA6Digital_IOSignal terminal OSC2/CLKO/RA6 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: OSC2/CLKO/RA6. Supported peripheral buses: RTC/CLK.
11RC0/T1OSO/T13CKIDigital_IOSignal terminal RC0/T1OSO/T13CKI (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC0/T1OSO/T13CKI. Supported peripheral buses: General.
12RC1/T1OSI/CCP2Digital_IOSignal terminal RC1/T1OSI/CCP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC1/T1OSI/CCP2. Supported peripheral buses: General.
13RC2/CCP1Digital_IOSignal terminal RC2/CCP1 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC2/CCP1. Supported peripheral buses: General.
14RC3/SCK/SCLDigital_IOSignal terminal RC3/SCK/SCL (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC3/SCK/SCL. Supported peripheral buses: SPI, I2C.
15RC4/SDI/SDADigital_IOSignal terminal RC4/SDI/SDA (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC4/SDI/SDA. Supported peripheral buses: I2C.
16RC5/SDODigital_IOSignal terminal RC5/SDO (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC5/SDO. Supported peripheral buses: General.
17RC6/TX/CKDigital_IOSignal terminal RC6/TX/CK (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC6/TX/CK. Supported peripheral buses: General.
18RC7/RX/DTDigital_IOSignal terminal RC7/RX/DT (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RC7/RX/DT. Supported peripheral buses: General.
19VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
20VDDPower_InPrimary positive power supply input (VDD) operating in the 2.0V to 5.5V domain (Max rating: 5.5V).
21RB0/INT0/FLT0/AN12Digital_IOSignal terminal RB0/INT0/FLT0/AN12 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB0/INT0/FLT0/AN12. Supported peripheral buses: General.
22RB1/INT1/AN10Digital_IOSignal terminal RB1/INT1/AN10 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB1/INT1/AN10. Supported peripheral buses: General.
23RB2/INT2/AN8Digital_IOSignal terminal RB2/INT2/AN8 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB2/INT2/AN8. Supported peripheral buses: General.
24RB3/AN9/CCP2Digital_IOSignal terminal RB3/AN9/CCP2 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB3/AN9/CCP2. Supported peripheral buses: General.
25RB4/KBI0/AN11Digital_IOSignal terminal RB4/KBI0/AN11 (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB4/KBI0/AN11. Supported peripheral buses: General.
26RB5/KBI1/PGMDigital_IOSignal terminal RB5/KBI1/PGM (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB5/KBI1/PGM. Supported peripheral buses: General.
27RB6/KBI2/PGCDigital_IOSignal terminal RB6/KBI2/PGC (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB6/KBI2/PGC. Supported peripheral buses: General.
28RB7/KBI3/PGDDigital_IOSignal terminal RB7/KBI3/PGD (I/O, 2.0V to 5.5V domain). Multiplexed alternate functions: RB7/KBI3/PGD. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload