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MCP4261-104E/ML (QFN-16-EP(4x4)) — Symbol, Footprint IPC-7351B & 3D STEP Model

MCP4261-104E/ML

MICROCHIPID: C184659QFN-16-EP(4x4) · 17 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · MCP4261-104E/ML (QFN-16-EP(4x4))1CS2SCK3SDI4VSS5P0W6P0B7SDO8VDD9EP17EP16CS#15VDD14SDO13SHDN#12WP#11NC10P0BGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
1234567891011121314151617E=4.00mm · Pitch e=0.50mmD=4.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.00mm × 4.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (17/17)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1CSI/OMultiplexed I/O & Peripheral Pin CS (SPI)
2SCKI/OMultiplexed I/O & Peripheral Pin SCK (SPI)
3SDII/OMultiplexed I/O & Peripheral Pin SDI (SPI)
4VSSGNDGround Reference Pin (VSS)
5P0WI/OMultiplexed I/O & Peripheral Pin P0W (General)
6P0BI/OMultiplexed I/O & Peripheral Pin P0B (General)
7SDOI/OMultiplexed I/O & Peripheral Pin SDO (SPI)
8VDDPowerPower Supply Input (VDD — 2.7V to 5.5V)
9EPGNDExposed Thermal & Ground Pad (EP)
10P0BI/OMultiplexed I/O & Peripheral Pin P0B (General)
11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
12WP#I/OMultiplexed I/O & Peripheral Pin WP# (General)
13SHDN#I/OMultiplexed I/O & Peripheral Pin SHDN# (General)
14SDOI/OMultiplexed I/O & Peripheral Pin SDO (SPI)
15VDDPowerPower Supply Input (VDD — 2.7V to 5.5V)
16CS#I/OMultiplexed I/O & Peripheral Pin CS# (General)
17EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 CS
I/O
Multiplexed I/O & Peripheral Pin CS (SPI)
Design note: SPIChipSelectInput
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: MCP4261-104E/ML (MICROCHIP · QFN-16-EP(4x4))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
MCP4261-104E/ML (QFN-16-EP(4x4)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
MCP4261-104E/ML (QFN-16-EP(4x4)) - 2. Standard Pinout (Top View)
True package pinout (17 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
MCP4261-104E/ML (QFN-16-EP(4x4)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
MCP4261-104E/ML (QFN-16-EP(4x4)) - 4. Package Dimensions (D×E×A)
QFN-16-EP(4x4) · 4.00×4.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
MCP4261-104E/ML (QFN-16-EP(4x4)) - 5. Recommended Land Pattern
IPC-7351B Footprint (17 Pads)Expand ›
6. Application SchematicSCHEMATIC
MCP4261-104E/ML (QFN-16-EP(4x4)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for MCP4161 / MCP4261
P1 · p01_fig01867×1793px
MCP4261-104E/ML (QFN-16-EP(4x4)) — © 2008 Microchip Technology Inc. DS22059B-page 1
© 2008 Microchip Technology Inc. DS22059B-page 1
P2 · p02_fig011636×1340px
MCP4261-104E/ML (QFN-16-EP(4x4)) — POR Wiper
POR Wiper
P60 · p60_fig011777×695px
MCP4261-104E/ML (QFN-16-EP(4x4)) — FIGURE 8-4: MCP4XXX Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage. 8.3 Using Shutdown Modes
FIGURE 8-4: MCP4XXX Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage. 8.3 Using Shutdown Modes
P60 · p60_fig021576×608px
MCP4261-104E/ML (QFN-16-EP(4x4)) — FIGURE 8-3: Using the TC1240A to generate the VIHH voltage.
FIGURE 8-3: Using the TC1240A to generate the VIHH voltage.
P60 · p60_fig03867×1140px
MCP4261-104E/ML (QFN-16-EP(4x4)) — FIGURE 8-3: Using the TC1240A to generate the VIHH voltage.
FIGURE 8-3: Using the TC1240A to generate the VIHH voltage.
P60 · p60_fig01P60
MCP4261-104E/ML (QFN-16-EP(4x4)) — Datasheet Page 60 (p60_fig01)
Datasheet Page 60 (p60_fig01)
P61 · p61_fig011778×1123px
MCP4261-104E/ML (QFN-16-EP(4x4)) — FIGURE 8-6: Typical Microcontroller Connections.
FIGURE 8-6: Typical Microcontroller Connections.
P65 · p65_fig021777×754px
MCP4261-104E/ML (QFN-16-EP(4x4)) — © 2008 Microchip Technology Inc. DS22059B-page 65 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spec
© 2008 Microchip Technology Inc. DS22059B-page 65 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-spec
P65 · p65_fig02P65
MCP4261-104E/ML (QFN-16-EP(4x4)) — Datasheet Page 65 (p65_fig02)
Datasheet Page 65 (p65_fig02)
P65 · p65_fig01All Packages in PDF
MCP4261-104E/ML (QFN-16-EP(4x4)) — MCP414X/416X/424X/426X | 10.0 PACKAGING INFORMATION | 10.1 Package Marking Information | 8-Lead DFN (3x3) Example: Part Number Code Part Number Code | MCP4141-502E/MF DAAJ MCP4142-502E/MF DABC | MCP4141-103E/MF DAAK MCP4142-103E/MF DABD | M
MCP414X/416X/424X/426X | 10.0 PACKAGING INFORMATION | 10.1 Package Marking Information | 8-Lead DFN (3x3) Example: Part Number Code Part Number Code | MCP4141-502E/MF DAAJ MCP4142-502E/MF DABC | MCP4141-103E/MF DAAK MCP4142-103E/MF DABD | M
P72 · p72_fig01All Packages in PDF
MCP4261-104E/ML (QFN-16-EP(4x4)) — MCP414X/416X/424X/426X - 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] - Note: For the most current package drawings, please see the Microchip Packaging Specification located at | MCP414X/416X/424X/426X | DS22059B-page 72
MCP414X/416X/424X/426X - 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] - Note: For the most current package drawings, please see the Microchip Packaging Specification located at | MCP414X/416X/424X/426X | DS22059B-page 72
P73 · p73_fig01All Packages in PDF
MCP4261-104E/ML (QFN-16-EP(4x4)) — © 2008 Microchip Technology Inc. DS22059B-page 73
© 2008 Microchip Technology Inc. DS22059B-page 73

Technical Specifications & Part Details (MCP4261-104E/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:MCP4261-104E/ML (QFN-16-EP(4x4)) is a 16-pin standard electronic & interconnect component featuring a 4.00 × 4.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.7V to 5.5V supply operation across 0°C to 70°C with integrated SPI interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
0°C to 70°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
10 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.00 × 4.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-16-EP(4x4))
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol17 auto-grouped pins
OK
IPC-7351B Land Pattern17 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 2.70×2.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-16-EP(4x4))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.00 × 4.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
17P / 17Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-16-EP(4x4)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — MCP4261-104E/ML (QFN-16-EP(4x4))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of MCP4261-104E/ML (QFN-16-EP(4x4))?

Manufactured by MICROCHIP, the MCP4261-104E/ML is housed in a QFN-16-EP(4x4) package with 17 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.7V to 5.5V. Key pins include: 1 (CS: Multiplexed I/O & Peripheral Pin CS (SPI)), 2 (SCK: Multiplexed I/O & Peripheral Pin SCK (SPI)), 3 (SDI: Multiplexed I/O & Peripheral Pin SDI (SPI)), 4 (VSS: Ground Reference Pin (VSS)), 5 (P0W: Multiplexed I/O & Peripheral Pin P0W (General)), 6 (P0B: Multiplexed I/O & Peripheral Pin P0B (General)).

What are the IPC-7351B PCB Footprint dimensions for MCP4261-104E/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), MCP4261-104E/ML (QFN-16-EP(4x4)) has a nominal body envelope of 4.00 × 4.00 mm, pitch e = 0.50 mm, and 17 copper pads plus a central exposed thermal pad (EPAD) of 2.70 × 2.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for MCP4261-104E/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for MCP4261-104E/ML (MICROCHIP, QFN-16-EP(4x4)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (17 pins) & MCP4161 / MCP4261 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1CSDigital_IOSignal terminal CS (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SPICHIPSELECTINPUT. Supported peripheral buses: SPI.
2SCKDigital_IOSignal terminal SCK (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SPICLOCKINPUT. Supported peripheral buses: SPI.
3SDIDigital_IOSignal terminal SDI (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SPISERIALDATAINPUT. Supported peripheral buses: SPI.
4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
5P0WDigital_IOSignal terminal P0W (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0W. Supported peripheral buses: General.
6P0BDigital_IOSignal terminal P0B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0B. Supported peripheral buses: General.
7SDODigital_IOSignal terminal SDO (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SPISERIALDATAOUT. Supported peripheral buses: SPI.
8VDDPower_InPrimary positive power supply input (VDD) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
9EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
10P0BDigital_IOSignal terminal P0B (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0B. Supported peripheral buses: General.
11NCNCSignal terminal NC (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
12WP#Digital_IOSignal terminal WP# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: WP#. Supported peripheral buses: General.
13SHDN#Digital_IOSignal terminal SHDN# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SHDN#. Supported peripheral buses: General.
14SDODigital_IOSignal terminal SDO (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: SPISERIALDATAOUT. Supported peripheral buses: SPI.
15VDDPower_InPrimary positive power supply input (VDD) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
16CS#Digital_IOSignal terminal CS# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
17EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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