DN3135K1-G (SOT-23) — Schematic Symbol, IPC-7351B Footprint & 3D STEP Model

Q: What is the Pinout and operating voltage specification of DN3135K1-G (SOT-23)?

Manufactured by MICROCHIP, the DN3135K1-G is housed in a SOT-23 package with 3 pins and a 1.90 mm lead pitch. Key pins include: 1 (Gate: Multiplexed I/O & Peripheral Pin Gate (General)), 2 (Source: Multiplexed I/O & Peripheral Pin Source (General)), 3 (Drain: Multiplexed I/O & Peripheral Pin Drain (General)).

Q: What are the IPC-7351B PCB Footprint dimensions for DN3135K1-G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), DN3135K1-G (SOT-23) has a nominal body envelope of 1.30 × 2.90 mm, pitch e = 1.90 mm, and 3 copper pads.

Q: Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for DN3135K1-G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for DN3135K1-G (MICROCHIP, SOT-23) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

1. SYMBOL

2. 2D FOOTPRINT

3. 3D CAD MODEL

Package Body: 2.90mm × 1.30mm · Pitch: 1.90mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (3/3)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D

Pin	Symbol	Type	Function (EN)
1	Gate	I/O	Multiplexed I/O & Peripheral Pin Gate (General)
2	Source	I/O	Multiplexed I/O & Peripheral Pin Source (General)
3	Drain	Analog	Multiplexed I/O & Peripheral Pin Drain (General)

PIN 1 Gate

I/O

Multiplexed I/O & Peripheral Pin Gate (General)

Design note: Gate

IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 9 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen

1. Realistic 3D PackageREPRESENTATIVE

DN3135K1-G (SOT-23) - 1. Realistic 3D Package

Detailed solid 3D bodyExpand ›

2. Standard Pinout (Top View)CLEANROOM PINOUT

DN3135K1-G (SOT-23) - 2. Standard Pinout (Top View)

True package pinout (3 pins)Expand ›

3. Original Datasheet PinoutPDF PINOUT

DN3135K1-G (SOT-23) - 3. Original Datasheet Pinout

Uncropped datasheet pin diagramExpand ›

4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS

DN3135K1-G (SOT-23) - 4. Package Dimensions (D×E×A)

SOT-23 · 2.90×1.30mm · Pitch 1.90mmExpand ›

5. Recommended Land PatternLAND PATTERN

DN3135K1-G (SOT-23) - 5. Recommended Land Pattern

IPC-7351B Footprint (3 Pads)Expand ›

6. Application SchematicSCHEMATIC

DN3135K1-G (SOT-23) - 6. Application Schematic

Typical Application SchematicExpand ›

Original Datasheet Pinouts & Technical Drawings (9 figures · Page 1/1)

Showing 1–9 of 9 uncropped original figures for DN3135

P6 · p06_fig01EXACT PACKAGE

XXXNNN N1S894 | 3-lead SOT-23 Example | 3-lead SOT-89 Example | XXXXYWW NNN | DN1S732 987

P7 · p07_fig01EXACT PACKAGE

DN3135K1-G (SOT-23) — 3-Lead TO-236AB (SOT-23) Package Outline (K1/T) 2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch | Symbol A A1 A2 b D E E1 e e1 L L1 ș | Dimension | (mm) | MIN 0.89 0.01 0.88 0.30 2.80 2.10 1.20 0.95 BSC | 1.90 BSC | 0.20† 0.54 REF | 0O

3-Lead TO-236AB (SOT-23) Package Outline (K1/T) 2.90x1.30mm body, 1.12mm height (max), 1.90mm pitch | Symbol A A1 A2 b D E E1 e e1 L L1 ș | Dimension | (mm) | MIN 0.89 0.01 0.88 0.30 2.80 2.10 1.20 0.95 BSC | 1.90 BSC | 0.20† 0.54 REF | 0O

P1 · p01_fig01376×200px

N-Channel Depletion-Mode Vertical DMOS FET

P1 · p01_fig02300×270px

See Table 2-1 for pin information.

P1 · p01_fig03287×261px

(Top view)

P1 · p01_fig02P1

Datasheet Page 1 (p01_fig02)

P6 · p06_fig021777×964px

DS20005703A-page 6  2017 Microchip Technology Inc. | 3 e | 3 e

P7 · p07_fig01P7

Datasheet Page 7 (p07_fig01)

P8 · p08_fig01All Packages in PDF

DN3135K1-G (SOT-23) — 3-Lead TO-243AA (SOT-89) Package Outline (N8) | Symbol A b b1 C D D1 E E1 e e1 H L | Dimensions | (mm) | MIN 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.00† | 1.50 BSC | 3.00 BSC | 3.94 0.73† | NOM - - - - - - - - - - | MAX 1.60 0.56 0.48 0.44 4.6

3-Lead TO-243AA (SOT-89) Package Outline (N8) | Symbol A b b1 C D D1 E E1 e e1 H L | Dimensions | (mm) | MIN 1.40 0.44 0.36 0.35 4.40 1.62 2.29 2.00† | 1.50 BSC | 3.00 BSC | 3.94 0.73† | NOM - - - - - - - - - - | MAX 1.60 0.56 0.48 0.44 4.6

Technical Specifications & Part Details (DN3135K1-G)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)

Standard Electronic & Interconnect Component

Detailed Overview:DN3135K1-G (SOT-23) is a 3-pin standard electronic & interconnect component featuring a 2.90 × 1.30 × 1.10 mm mechanical envelope (lead pitch e = 1.90 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across 55°C to +150°C with integrated Standard I/O / Passive interfaces.

Operating Supply VoltageV_CC / V_DD

1.8V ~ 5.5V (Theo Datasheet)

Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins

Ambient Operating TemperatureT_A

55°C to +150°C

Industrial temperature grade; T_J(max) = +125°C

Clock / RF Operating Frequencyf_CLK / f_RF

1 MHz

Extracted from authoritative PDF specification tables

Current & Power RatingI_OUT / I_CC

I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA

Observe per-pin absolute maximum current limits

Package Envelope (D × E × A)D × E × A

2.90 × 1.30 × 1.10 mm (A1=0.07 mm)

Package family: SOT23 (SOT-23)

Pin Count & Lead PitchN / e

3 Pins | Pitch e = 1.90 mm (74.8 mil)

Normalized to Center-to-Center Span C per IPC-7351B

Integrated Peripheral InterfacesBuses

Standard I/O / Passive

Cross-linked with 4D Pinout & Schematic Symbol

Reflow & Moisture SensitivityIPC / MSL

IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3

60% windowed solder paste stencil on thermal EPAD

Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.

Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export

5/5 PASS

IEEE-315 Symbol3 auto-grouped pins

IPC-7351B Land Pattern3 pads · Pitch 1.90mm

IPC-7525 60% Solder PasteReflow 1:1 Standard

DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm

3D STEP AP214 & GLBAligned coordinate origin (0,0,0)

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet

5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOT-23)

Extracted from Datasheet & IPC-7351B Normalized

Package Body (D × E)Nominal

2.90 × 1.30 mm

Height (A) & Pitch (e)IPC-7351B

A=1.10mm · e=1.90mm

Pad Size (W × L)Level B

0.65 × 1.00 mm

Pins / Total PadsTopology

3P / 3Pad (SOT_SMALL)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives

DFM READY

Designator / Replacement MPN	Value / Package	Function & PCB Layout Rule
N/A BOM	Per application circuit SOT-23	Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — DN3135K1-G (SOT-23)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats

IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of DN3135K1-G (SOT-23)?

Manufactured by MICROCHIP, the DN3135K1-G is housed in a SOT-23 package with 3 pins and a 1.90 mm lead pitch. Key pins include: 1 (Gate: Multiplexed I/O & Peripheral Pin Gate (General)), 2 (Source: Multiplexed I/O & Peripheral Pin Source (General)), 3 (Drain: Multiplexed I/O & Peripheral Pin Drain (General)).

What are the IPC-7351B PCB Footprint dimensions for DN3135K1-G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), DN3135K1-G (SOT-23) has a nominal body envelope of 1.30 × 2.90 mm, pitch e = 1.90 mm, and 3 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for DN3135K1-G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for DN3135K1-G (MICROCHIP, SOT-23) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (3 pins) & DN3135 Family VariantsExpand static table

Pin #	Signal Name	Electrical Type	Functional Description & Design Notes
1	Gate	Digital_IO	Signal terminal Gate (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Gate. Supported peripheral buses: General.
2	Source	Digital_IO	Signal terminal Source (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Source. Supported peripheral buses: General.
3	Drain	Analog	Signal terminal Drain (Analog, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: Drain. Supported peripheral buses: General.

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