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APT68GA60B2D40 (TO-247-3) — Symbol, Footprint IPC-7351B & 3D STEP Model

APT68GA60B2D40

MICROCHIPID: C17644884TO-247-3 · 3 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · APT68GA60B2D40 (TO-247-3)1G2C3EGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.810.25.10-5.1-10.2mm
2. 2D FOOTPRINT
123E=15.80mm · Pitch e=0.50mmD=5.00mm-12-10-8-6-4-20246810126420-2-4-6mm
3. 3D CAD MODEL
Package Body: 15.80mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (3/3)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GI/OMultiplexed I/O & Peripheral Pin G (General)
2CI/OMultiplexed I/O & Peripheral Pin C (General)
3EI/OMultiplexed I/O & Peripheral Pin E (General)
PIN 1 G
I/O
Multiplexed I/O & Peripheral Pin G (General)
Design note: Signal terminal G (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: G. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: APT68GA60B2D40 (MICROCHIP · TO-247-3)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
APT68GA60B2D40 (TO-247-3) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
APT68GA60B2D40 (TO-247-3) - 2. Standard Pinout (Top View)
True package pinout (3 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
APT68GA60B2D40 (TO-247-3) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
APT68GA60B2D40 (TO-247-3) - 4. Package Dimensions (D×E×A)
TO-247-3 · 15.80×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
APT68GA60B2D40 (TO-247-3) - 5. Recommended Land Pattern
IPC-7351B Footprint (3 Pads)Expand ›
6. Application SchematicSCHEMATIC
APT68GA60B2D40 (TO-247-3) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for APT68GA60B2D
P1 · p01_fig01690×179px
APT68GA60B2D40 (TO-247-3) — High Speed PT IGBT
High Speed PT IGBT
P1 · p01_fig02740×764px
APT68GA60B2D40 (TO-247-3) — TYPICAL APPLICATIONS
TYPICAL APPLICATIONS
P1 · p01_fig02P1
APT68GA60B2D40 (TO-247-3) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P4 · p04_fig011614×2632px
APT68GA60B2D40 (TO-247-3) — 0 | 5 | 10 | 15 | 20 | 25 | 30 | 0 20 40 60 80 0 | 50 | 100 | 150 | 200 | 250 | 0 10 20 30 40 50 60 70 80 | 0 | 500 | 1000 | 1500 | 2000 | 2500 | 3000 | 0 25 50 75 100 125 0 | 1000 | 2000 | 3000 | 4000 | 5000 | 6000 | 7000 | 8000 | 0 10 20
0 | 5 | 10 | 15 | 20 | 25 | 30 | 0 20 40 60 80 0 | 50 | 100 | 150 | 200 | 250 | 0 10 20 30 40 50 60 70 80 | 0 | 500 | 1000 | 1500 | 2000 | 2500 | 3000 | 0 25 50 75 100 125 0 | 1000 | 2000 | 3000 | 4000 | 5000 | 6000 | 7000 | 8000 | 0 10 20
P9 · p09_fig011725×587px
APT68GA60B2D40 (TO-247-3) — Figure 31. Diode Test Circuit
Figure 31. Diode Test Circuit
P9 · p09_fig021924×515px
APT68GA60B2D40 (TO-247-3) — Figure 31. Diode Test Circuit
Figure 31. Diode Test Circuit
P9 · p09_fig031882×895px
APT68GA60B2D40 (TO-247-3) — T-MAXTM (B2) Package Outline TO-264 (L) Package Outline
T-MAXTM (B2) Package Outline TO-264 (L) Package Outline
P9 · p09_fig03P9
APT68GA60B2D40 (TO-247-3) — Datasheet Page 9 (p09_fig03)
Datasheet Page 9 (p09_fig03)

Technical Specifications & Part Details (APT68GA60B2D40)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:APT68GA60B2D40 (TO-247-3) is a 3-pin standard electronic & interconnect component featuring a 15.80 × 5.00 × 2.00 mm mechanical envelope (lead pitch e = 0.00 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
15.80 × 5.00 × 2.00 mm (A1=0.02 mm)
Package family: OTHER (TO-247-3)
Pin Count & Lead PitchN / e
3 Pins
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol3 auto-grouped pins
OK
IPC-7351B Land Pattern3 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 13.68×2.20mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TO-247-3)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
15.80 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=2.00mm · e=0.50mm
Pad Size (W × L)Level B
0.40 × 0.90 mm
Pins / Total PadsTopology
3P / 3Pad (CUSTOM_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TO-247-3
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — APT68GA60B2D40 (TO-247-3)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of APT68GA60B2D40 (TO-247-3)?

Manufactured by MICROCHIP, the APT68GA60B2D40 is housed in a TO-247-3 package with 3 pins and a 0.50 mm lead pitch. Key pins include: 1 (G: Multiplexed I/O & Peripheral Pin G (General)), 2 (C: Multiplexed I/O & Peripheral Pin C (General)), 3 (E: Multiplexed I/O & Peripheral Pin E (General)).

What are the IPC-7351B PCB Footprint dimensions for APT68GA60B2D40?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), APT68GA60B2D40 (TO-247-3) has a nominal body envelope of 5.00 × 15.80 mm, pitch e = 0.50 mm, and 3 copper pads plus a central exposed thermal pad (EPAD) of 13.68 × 2.20 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for APT68GA60B2D40?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for APT68GA60B2D40 (MICROCHIP, TO-247-3) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (3 pins) & APT68GA60B2D Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GDigital_IOSignal terminal G (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: G. Supported peripheral buses: General.
2CDigital_IOSignal terminal C (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: C. Supported peripheral buses: General.
3EDigital_IOSignal terminal E (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: E. Supported peripheral buses: General.
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