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C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) — Symbol, Footprint IPC-7351B & 3D STEP Model

C17384612

SemiconductorPLCC-20_L9.0-W9.0-P1.27-LS9.9-T · 20 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T)1NC2DATA3NC4DCLK5WP16NC7NC8(WP)RESET/OE9nCS10GND20VCC19NC18SER_EN#17NC16NC15READY14NC13NC12(A2)nCASC11NCGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
2019321678451112139101617181415E=9.00mm · Pitch e=1.27mmD=9.00mm-8-6-4-20246886420-2-4-6-8mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NCI/OMultiplexed I/O & Peripheral Pin NC (General)
2DATAI/OMultiplexed I/O & Peripheral Pin DATA (General)
3NCI/OMultiplexed I/O & Peripheral Pin NC (General)
4DCLKI/OMultiplexed I/O & Peripheral Pin DCLK (General)
5WP1I/OMultiplexed I/O & Peripheral Pin WP1 (General)
6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
8(WP)RESET/OE#ISystem Enable & Hardware Reset ((WP)RESET/OE#)
9nCSI/OMultiplexed I/O & Peripheral Pin nCS (General)
10GNDGNDGround Reference Pin (GND)
11NCI/OMultiplexed I/O & Peripheral Pin NC (General)
12(A2)nCASCI/OMultiplexed I/O & Peripheral Pin (A2)nCASC (General)
13NCI/OMultiplexed I/O & Peripheral Pin NC (General)
14NCI/OMultiplexed I/O & Peripheral Pin NC (General)
15READYI/OMultiplexed I/O & Peripheral Pin READY (General)
16NCI/OMultiplexed I/O & Peripheral Pin NC (General)
17NCI/OMultiplexed I/O & Peripheral Pin NC (General)
18SER_EN#I/OMultiplexed I/O & Peripheral Pin SER_EN# (General)
19NCI/OMultiplexed I/O & Peripheral Pin NC (General)
20VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
PIN 1 NC
I/O
Multiplexed I/O & Peripheral Pin NC (General)
Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C17384612 (Semiconductor · PLCC-20_L9.0-W9.0-P1.27-LS9.9-T)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) - 4. Package Dimensions (D×E×A)
PLCC-20_L9.0-W9.0-P1.27-LS9.9-T · 9.00×9.00mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C17384612)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) is a 20-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 1.15 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 1.15 mm (A1=0.03 mm)
Package family: LGA (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T)
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.15mm · e=1.27mm
Pad Size (W × L)Level B
0.64 × 2.45 mm
Pins / Total PadsTopology
20P / 20Pad (LGA_ARRAY)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PLCC-20_L9.0-W9.0-P1.27-LS9.9-T
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T)?

Manufactured by Semiconductor, the C17384612 is housed in a PLCC-20_L9.0-W9.0-P1.27-LS9.9-T package with 20 pins and a 1.27 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (DATA: Multiplexed I/O & Peripheral Pin DATA (General)), 3 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 4 (DCLK: Multiplexed I/O & Peripheral Pin DCLK (General)), 5 (WP1: Multiplexed I/O & Peripheral Pin WP1 (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for C17384612?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C17384612 (PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 1.27 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C17384612?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C17384612 (Semiconductor, PLCC-20_L9.0-W9.0-P1.27-LS9.9-T) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & AT17LV512A Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2DATADigital_IOSignal terminal DATA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DATA. Supported peripheral buses: General.
3NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
4DCLKDigital_IOSignal terminal DCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCLK. Supported peripheral buses: General.
5WP1Digital_IOSignal terminal WP1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WP1. Supported peripheral buses: General.
6NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8(WP)RESET/OE#Digital_IOActive-low hardware reset terminal ((WP)RESET/OE#): pulling this pin Low resets the processor core and peripherals.
9nCSDigital_IOSignal terminal nCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: nCS. Supported peripheral buses: General.
10GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
11NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
12(A2)nCASCDigital_IOSignal terminal (A2)nCASC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: (A2)nCASC. Supported peripheral buses: General.
13NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
14NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
15READYDigital_IOSignal terminal READY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: READY. Supported peripheral buses: General.
16NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
17NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
18SER_EN#Digital_IOSignal terminal SER_EN# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SER_EN#. Supported peripheral buses: General.
19NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
20VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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