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C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) — Symbol, Footprint IPC-7351B & 3D STEP Model

C167319

SemiconductorDIP-24_L31.0-W5.3-P2.54-LS9.6-BL · 24 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL)1SEG72VCC3DOUT4LOAD5DIN6DCLK7DIG78DIG69DIG510DIG411DIG312DIG224SEG623SEG522SEG421SEG320SEG219SEG118SEG017NC.16RST15GND14DIG013DIG1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.220.315.210.25.10-5.1-10.2-15.2-20.3mm
2. 2D FOOTPRINT
132122232420191817161514111210123456789E=31.00mm · Pitch e=2.54mmD=5.30mm-24-22-20-18-16-14-12-10-8-6-4-2024681012141618202224131197531-1-3-5-7-9-11-13mm
3. 3D CAD MODEL
Package Body: 31.00mm × 5.30mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (24/24)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1SEG7I/OMultiplexed I/O & Peripheral Pin SEG7 (General)
2VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
3DOUTI/OMultiplexed I/O & Peripheral Pin DOUT (General)
4LOADI/OMultiplexed I/O & Peripheral Pin LOAD (General)
5DINI/OMultiplexed I/O & Peripheral Pin DIN (General)
6DCLKI/OMultiplexed I/O & Peripheral Pin DCLK (General)
7DIG7I/OMultiplexed I/O & Peripheral Pin DIG7 (General)
8DIG6I/OMultiplexed I/O & Peripheral Pin DIG6 (General)
9DIG5I/OMultiplexed I/O & Peripheral Pin DIG5 (General)
10DIG4I/OMultiplexed I/O & Peripheral Pin DIG4 (General)
11DIG3I/OMultiplexed I/O & Peripheral Pin DIG3 (General)
12DIG2I/OMultiplexed I/O & Peripheral Pin DIG2 (General)
13DIG1I/OMultiplexed I/O & Peripheral Pin DIG1 (General)
14DIG0I/OMultiplexed I/O & Peripheral Pin DIG0 (General)
15GNDGNDGround Reference Pin (GND)
16RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
17NC.I/OMultiplexed I/O & Peripheral Pin NC. (General)
18SEG0I/OMultiplexed I/O & Peripheral Pin SEG0 (General)
19SEG1I/OMultiplexed I/O & Peripheral Pin SEG1 (General)
20SEG2I/OMultiplexed I/O & Peripheral Pin SEG2 (General)
21SEG3I/OMultiplexed I/O & Peripheral Pin SEG3 (General)
22SEG4I/OMultiplexed I/O & Peripheral Pin SEG4 (General)
23SEG5I/OMultiplexed I/O & Peripheral Pin SEG5 (General)
24SEG6I/OMultiplexed I/O & Peripheral Pin SEG6 (General)
PIN 1 SEG7
I/O
Multiplexed I/O & Peripheral Pin SEG7 (General)
Design note: Signal terminal SEG7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG7. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C167319 (Semiconductor · DIP-24_L31.0-W5.3-P2.54-LS9.6-BL)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) - 2. Standard Pinout (Top View)
True package pinout (24 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) - 4. Package Dimensions (D×E×A)
DIP-24_L31.0-W5.3-P2.54-LS9.6-BL · 31.00×5.30mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) - 5. Recommended Land Pattern
IPC-7351B Footprint (24 Pads)Expand ›
6. Application SchematicSCHEMATIC
C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C167319)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) is a 24-pin standard electronic & interconnect component featuring a 8.62 × 28.94 × 3.85 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.62 × 28.94 × 3.85 mm (A1=0.51 mm)
Package family: DIP (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL)
Pin Count & Lead PitchN / e
24 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol24 auto-grouped pins
OK
IPC-7351B Land Pattern24 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
31.00 × 5.30 mm
Height (A) & Pitch (e)IPC-7351B
A=3.85mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
24P / 24Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
DIP-24_L31.0-W5.3-P2.54-LS9.6-BL
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL)?

Manufactured by Semiconductor, the C167319 is housed in a DIP-24_L31.0-W5.3-P2.54-LS9.6-BL package with 24 pins and a 2.54 mm lead pitch. Key pins include: 1 (SEG7: Multiplexed I/O & Peripheral Pin SEG7 (General)), 2 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 3 (DOUT: Multiplexed I/O & Peripheral Pin DOUT (General)), 4 (LOAD: Multiplexed I/O & Peripheral Pin LOAD (General)), 5 (DIN: Multiplexed I/O & Peripheral Pin DIN (General)), 6 (DCLK: Multiplexed I/O & Peripheral Pin DCLK (General)).

What are the IPC-7351B PCB Footprint dimensions for C167319?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C167319 (DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) has a nominal body envelope of 5.30 × 31.00 mm, pitch e = 2.54 mm, and 24 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C167319?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C167319 (Semiconductor, DIP-24_L31.0-W5.3-P2.54-LS9.6-BL) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (24 pins) & CH451 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1SEG7Digital_IOSignal terminal SEG7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG7. Supported peripheral buses: General.
2VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3DOUTDigital_IOSignal terminal DOUT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DOUT. Supported peripheral buses: General.
4LOADDigital_IOSignal terminal LOAD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: LOAD. Supported peripheral buses: General.
5DINDigital_IOSignal terminal DIN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIN. Supported peripheral buses: General.
6DCLKDigital_IOSignal terminal DCLK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCLK. Supported peripheral buses: General.
7DIG7Digital_IOSignal terminal DIG7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG7. Supported peripheral buses: General.
8DIG6Digital_IOSignal terminal DIG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG6. Supported peripheral buses: General.
9DIG5Digital_IOSignal terminal DIG5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG5. Supported peripheral buses: General.
10DIG4Digital_IOSignal terminal DIG4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG4. Supported peripheral buses: General.
11DIG3Digital_IOSignal terminal DIG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG3. Supported peripheral buses: General.
12DIG2Digital_IOSignal terminal DIG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG2. Supported peripheral buses: General.
13DIG1Digital_IOSignal terminal DIG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG1. Supported peripheral buses: General.
14DIG0Digital_IOSignal terminal DIG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG0. Supported peripheral buses: General.
15GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
16RSTDigital_IOSignal terminal RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST. Supported peripheral buses: General.
17NC.Digital_IOSignal terminal NC. (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC.. Supported peripheral buses: General.
18SEG0Digital_IOSignal terminal SEG0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG0. Supported peripheral buses: General.
19SEG1Digital_IOSignal terminal SEG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG1. Supported peripheral buses: General.
20SEG2Digital_IOSignal terminal SEG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG2. Supported peripheral buses: General.
21SEG3Digital_IOSignal terminal SEG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG3. Supported peripheral buses: General.
22SEG4Digital_IOSignal terminal SEG4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG4. Supported peripheral buses: General.
23SEG5Digital_IOSignal terminal SEG5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG5. Supported peripheral buses: General.
24SEG6Digital_IOSignal terminal SEG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG6. Supported peripheral buses: General.
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