Mechanical Dimensions & Land Pattern (QFN-32-EP(5x5))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-32-EP(5x5) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — ZL40209LDG1 (QFN-32-EP(5x5))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ZL40209LDG1 (QFN-32-EP(5x5))?
Manufactured by MICROCHIP, the ZL40209LDG1 is housed in a QFN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (vt0 vt1 ,: Multiplexed I/O & Peripheral Pin vt0 vt1 , (General)), 3 (ctrl0 ctrl1 ,: Multiplexed I/O & Peripheral Pin ctrl0 ctrl1 , (General)), 4 (NC: No Connect (Leave Floating)), 5 (IO2: GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1), 6 (vt0 vt1 ,: Multiplexed I/O & Peripheral Pin vt0 vt1 , (General)).
What are the IPC-7351B PCB Footprint dimensions for ZL40209LDG1?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ZL40209LDG1 (QFN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.50 × 3.50 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ZL40209LDG1?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ZL40209LDG1 (MICROCHIP, QFN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (33 pins) & ZL40209 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | IO1 | Digital_IO | General Purpose Digital I/O Pin IO1 |
| 2 | vt0 vt1 , | Digital_IO | Signal terminal vt0 vt1 , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: vt0 vt1 ,. Supported peripheral buses: General. |
| 3 | ctrl0 ctrl1 , | Digital_IO | Signal terminal ctrl0 ctrl1 , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ctrl0 ctrl1 ,. Supported peripheral buses: General. |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | IO2 | Digital_IO | GPIO2 / RTC_GPIO2 / TOUCH2 / ADC1_CH1 |
| 6 | vt0 vt1 , | Digital_IO | Signal terminal vt0 vt1 , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: vt0 vt1 ,. Supported peripheral buses: General. |
| 7 | ctrl0 ctrl1 , | Digital_IO | Signal terminal ctrl0 ctrl1 , (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ctrl0 ctrl1 ,. Supported peripheral buses: General. |
| 8 | IO0 | Digital_IO | GPIO0 / RTC_GPIO0 (Chip Boot Mode Strapping Pin) |
| 9 | gnd | GND | 0V electrical ground return terminal (gnd) for internal core logic, I/O drivers, and analog sub-blocks. |
| 10 | NC | NC | Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General. |
| 11 | vdd | Power_In | Primary positive power supply input (vdd) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 12 | IO7 | Digital_IO | GPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6 |
| 13 | IO15 | Digital_IO | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | Digital_IO | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | IO17 | Digital_IO | GPIO17 / RTC_GPIO17 / U1TXD / ADC2_CH6 |
| 16 | vdd | Power_In | Primary positive power supply input (vdd) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 17 | gnd | GND | 0V electrical ground return terminal (gnd) for internal core logic, I/O drivers, and analog sub-blocks. |
| 18 | vdd | Power_In | Primary positive power supply input (vdd) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 19 | IO20 | Digital_IO | GPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9 |
| 20 | IO9 | Digital_IO | GPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD |
| 21 | IO10 | Digital_IO | GPIO10 / RTC_GPIO10 / TOUCH10 / ADC1_CH9 / FSPICS0 |
| 22 | IO11 | Digital_IO | GPIO11 / RTC_GPIO11 / TOUCH11 / ADC2_CH0 / FSPID |
| 23 | vdd | Power_In | Primary positive power supply input (vdd) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 24 | gnd | GND | 0V electrical ground return terminal (gnd) for internal core logic, I/O drivers, and analog sub-blocks. |
| 25 | vdd | Power_In | Primary positive power supply input (vdd) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 26 | IO21 | Digital_IO | GPIO21 / RTC_GPIO21 |
| 27 | IO47 | Digital_IO | GPIO47 / SPICLK_P_DIFF / SUBSPICLK_P_DIFF |
| 28 | IO33 | Digital_IO | GPIO33 / FSPIHD / SUBSPIHD / SPIIO4 |
| 29 | IO29 | Digital_IO | General Purpose Digital I/O Pin IO29 |
| 30 | vdd | Power_In | Primary positive power supply input (vdd) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 31 | sel | Digital_IO | Signal terminal sel (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: sel. Supported peripheral buses: General. |
| 32 | gnd | GND | 0V electrical ground return terminal (gnd) for internal core logic, I/O drivers, and analog sub-blocks. |
| 33 | EPAD/GND | GND | 0V electrical ground return terminal (EPAD/GND) for internal core logic, I/O drivers, and analog sub-blocks. |