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C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0) — Symbol, Footprint IPC-7351B & 3D STEP Model

C1526199

SemiconductorWIRELM-SMD_MICROCHIP_ATWINC15X0 · 29 Pins · Pitch 1.02mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0)1GPIO_62I2C_SCL3I2C_SDA4RESET_N5NC6NC7NC8NC9GND_110SPI_CFG11WAKE12GND_213IRQN14UART_TXD15SPI_MOSI29PADDLE_GND28GND_327GPIO_526GPIO_425GPIO_3241P3V_TP23VDDIO22CHIP_EN21GPIO_120VBATT19UART_RXD18SPI_SCK17SPI_MISO16SPI_SSNGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.225.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
ANTENNA KEEPOUT (6.2mm)2919181716151413121110987654321282726252423222120E=14.80mm · Pitch e=1.02mmD=21.80mm-14-12-10-8-6-4-2024681012141715131197531-1-3-5-7-9-11-13-15-17mm
3. 3D CAD MODEL
Package Body: 14.80mm × 21.80mm · Pitch: 1.02mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1GPIO_6I/OMultiplexed I/O & Peripheral Pin GPIO_6 (General)
2I2C_SCLI/OMultiplexed I/O & Peripheral Pin I2C_SCL (I2C)
3I2C_SDAI/OMultiplexed I/O & Peripheral Pin I2C_SDA (I2C)
4RESET_NISystem Enable & Hardware Reset (RESET_N)
5NCI/OMultiplexed I/O & Peripheral Pin NC (General)
6NCI/OMultiplexed I/O & Peripheral Pin NC (General)
7NCI/OMultiplexed I/O & Peripheral Pin NC (General)
8NCI/OMultiplexed I/O & Peripheral Pin NC (General)
9GND_1GNDGround Reference Pin (GND_1)
10SPI_CFGI/OMultiplexed I/O & Peripheral Pin SPI_CFG (SPI)
11WAKEI/OMultiplexed I/O & Peripheral Pin WAKE (General)
12GND_2GNDGround Reference Pin (GND_2)
13IRQNI/OMultiplexed I/O & Peripheral Pin IRQN (General)
14UART_TXDI/OMultiplexed I/O & Peripheral Pin UART_TXD (UART)
15SPI_MOSII/OMultiplexed I/O & Peripheral Pin SPI_MOSI (SPI)
16SPI_SSNI/OMultiplexed I/O & Peripheral Pin SPI_SSN (SPI)
17SPI_MISOI/OMultiplexed I/O & Peripheral Pin SPI_MISO (SPI)
18SPI_SCKI/OMultiplexed I/O & Peripheral Pin SPI_SCK (SPI)
19UART_RXDI/OMultiplexed I/O & Peripheral Pin UART_RXD (UART)
20VBATTPowerPower Supply Input (VBATT — 3.3V / 5.0V Standard Logic)
21GPIO_1I/OMultiplexed I/O & Peripheral Pin GPIO_1 (General)
22CHIP_ENI/OMultiplexed I/O & Peripheral Pin CHIP_EN (General)
23VDDIOPowerPower Supply Input (VDDIO — 3.3V / 5.0V Standard Logic)
241P3V_TPI/OMultiplexed I/O & Peripheral Pin 1P3V_TP (General)
25GPIO_3I/OMultiplexed I/O & Peripheral Pin GPIO_3 (General)
26GPIO_4I/OMultiplexed I/O & Peripheral Pin GPIO_4 (General)
27GPIO_5I/OMultiplexed I/O & Peripheral Pin GPIO_5 (General)
28GND_3GNDGround Reference Pin (GND_3)
29PADDLE_GNDGNDGround Reference Pin (PADDLE_GND)
PIN 1 GPIO_6
I/O
Multiplexed I/O & Peripheral Pin GPIO_6 (General)
Design note: Signal terminal GPIO_6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO_6. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: C1526199 (Semiconductor · WIRELM-SMD_MICROCHIP_ATWINC15X0)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0) - 4. Package Dimensions (D×E×A)
WIRELM-SMD_MICROCHIP_ATWINC15X0 · 14.80×21.80mm · Pitch 1.02mmExpand ›
5. Recommended Land PatternLAND PATTERN
C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0) - 6. Application Schematic
Typical Application SchematicExpand ›

Technical Specifications & Part Details (C1526199)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Wireless Wi-Fi / Bluetooth LE SoC Module
Detailed Overview:C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0) is a 28-pin wireless wi-fi / bluetooth le soc module featuring a 21.80 × 14.80 × 2.40 mm mechanical envelope (lead pitch e = 1.02 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C, SPI, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
21.80 × 14.80 × 2.40 mm (A1=0.00 mm)
Package family: CASTELLATED_MODULE (WIRELM-SMD_MICROCHIP_ATWINC15X0)
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 1.02 mm (40.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C, SPI, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 1.02mm
OK
IPC-7525 60% Solder PasteEPAD 3.70×3.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (WIRELM-SMD_MICROCHIP_ATWINC15X0)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
21.80 × 14.80 mm
Height (A) & Pitch (e)IPC-7351B
A=2.40mm · e=1.02mm
Pad Size (W × L)Level B
0.80 × 2.00 mm
Pins / Total PadsTopology
29P / 29Pad (CASTELLATED_MODULE)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
WIRELM-SMD_MICROCHIP_ATWINC15X0
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0)?

Manufactured by Semiconductor, the C1526199 is housed in a WIRELM-SMD_MICROCHIP_ATWINC15X0 package with 29 pins and a 1.02 mm lead pitch. Key pins include: 1 (GPIO_6: Multiplexed I/O & Peripheral Pin GPIO_6 (General)), 2 (I2C_SCL: Multiplexed I/O & Peripheral Pin I2C_SCL (I2C)), 3 (I2C_SDA: Multiplexed I/O & Peripheral Pin I2C_SDA (I2C)), 4 (RESET_N: System Enable & Hardware Reset (RESET_N)), 5 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 6 (NC: Multiplexed I/O & Peripheral Pin NC (General)).

What are the IPC-7351B PCB Footprint dimensions for C1526199?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), C1526199 (WIRELM-SMD_MICROCHIP_ATWINC15X0) has a nominal body envelope of 14.80 × 21.80 mm, pitch e = 1.02 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 3.70 × 3.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for C1526199?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for C1526199 (Semiconductor, WIRELM-SMD_MICROCHIP_ATWINC15X0) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & C1526199 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1GPIO_6Digital_IOSignal terminal GPIO_6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO_6. Supported peripheral buses: General.
2I2C_SCLDigital_IOSignal terminal I2C_SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C_SCL. Supported peripheral buses: I2C.
3I2C_SDADigital_IOSignal terminal I2C_SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: I2C_SDA. Supported peripheral buses: I2C.
4RESET_NDigital_IOActive-low hardware reset terminal (RESET_N): pulling this pin Low resets the processor core and peripherals.
5NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
6NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
7NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
8NCDigital_IOSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
9GND_1GND0V electrical ground return terminal (GND_1) for internal core logic, I/O drivers, and analog sub-blocks.
10SPI_CFGDigital_IOSignal terminal SPI_CFG (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_CFG. Supported peripheral buses: SPI.
11WAKEDigital_IOSignal terminal WAKE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WAKE. Supported peripheral buses: General.
12GND_2GND0V electrical ground return terminal (GND_2) for internal core logic, I/O drivers, and analog sub-blocks.
13IRQNDigital_IOSignal terminal IRQN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: IRQN. Supported peripheral buses: General.
14UART_TXDDigital_IOSignal terminal UART_TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UART_TXD. Supported peripheral buses: UART.
15SPI_MOSIDigital_IOSignal terminal SPI_MOSI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_MOSI. Supported peripheral buses: SPI.
16SPI_SSNDigital_IOSignal terminal SPI_SSN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_SSN. Supported peripheral buses: SPI.
17SPI_MISODigital_IOSignal terminal SPI_MISO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_MISO. Supported peripheral buses: SPI.
18SPI_SCKDigital_IOSignal terminal SPI_SCK (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI_SCK. Supported peripheral buses: SPI.
19UART_RXDDigital_IOSignal terminal UART_RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: UART_RXD. Supported peripheral buses: UART.
20VBATTPower_InPrimary positive power supply input (VBATT) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
21GPIO_1Digital_IOSignal terminal GPIO_1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO_1. Supported peripheral buses: General.
22CHIP_ENDigital_IOSignal terminal CHIP_EN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CHIP_EN. Supported peripheral buses: General.
23VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
241P3V_TPDigital_IOSignal terminal 1P3V_TP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: 1P3V_TP. Supported peripheral buses: General.
25GPIO_3Digital_IOSignal terminal GPIO_3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO_3. Supported peripheral buses: General.
26GPIO_4Digital_IOSignal terminal GPIO_4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO_4. Supported peripheral buses: General.
27GPIO_5Digital_IOSignal terminal GPIO_5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPIO_5. Supported peripheral buses: General.
28GND_3GND0V electrical ground return terminal (GND_3) for internal core logic, I/O drivers, and analog sub-blocks.
29PADDLE_GNDGND0V electrical ground return terminal (PADDLE_GND) for internal core logic, I/O drivers, and analog sub-blocks.
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