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AT86RF231-ZU (QFN-32-EP(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT86RF231-ZU

MICROCHIPID: C1526138QFN-32-EP(5x5) · 33 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT86RF231-ZU (QFN-32-EP(5x5))1DIG32DIG43AVSS4RFP5RFN6AVSS7DVSS8/RST9DIG110DIG211SLP_TR12DVSS13DVDD14DVDD15DEVDD16DVSS17CLKM33EP32AVSS31AVSS30AVSS29AVDD28EVDD27AVSS26XTAL125XTAL224IRQ23/SEL22MOSI21DVSS20MISO19SCLK18DVSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.827.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233E=5.00mm · Pitch e=0.50mmD=5.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (33/33)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DIG3I/OMultiplexed I/O & Peripheral Pin DIG3 (General)
2DIG4I/OMultiplexed I/O & Peripheral Pin DIG4 (General)
3AVSSGNDGround Reference Pin (AVSS)
4RFPI/OMultiplexed I/O & Peripheral Pin RFP (General)
5RFNI/OMultiplexed I/O & Peripheral Pin RFN (General)
6AVSSGNDGround Reference Pin (AVSS)
7DVSSGNDGround Reference Pin (DVSS)
8/RSTI/OMultiplexed I/O & Peripheral Pin /RST (General)
9DIG1I/OMultiplexed I/O & Peripheral Pin DIG1 (General)
10DIG2I/OMultiplexed I/O & Peripheral Pin DIG2 (General)
11SLP_TRI/OMultiplexed I/O & Peripheral Pin SLP_TR (General)
12DVSSGNDGround Reference Pin (DVSS)
13DVDDPowerPower Supply Input (DVDD — 1.8V to 3.6V)
14DVDDPowerPower Supply Input (DVDD — 1.8V to 3.6V)
15DEVDDPowerPower Supply Input (DEVDD — 1.8V to 3.6V)
16DVSSGNDGround Reference Pin (DVSS)
17CLKMI/OMultiplexed I/O & Peripheral Pin CLKM (General)
18DVSSGNDGround Reference Pin (DVSS)
19SCLKI/OMultiplexed I/O & Peripheral Pin SCLK (SPI, I2C)
20MISOI/OMultiplexed I/O & Peripheral Pin MISO (SPI)
21DVSSGNDGround Reference Pin (DVSS)
22MOSII/OMultiplexed I/O & Peripheral Pin MOSI (SPI)
23/SELI/OMultiplexed I/O & Peripheral Pin /SEL (SPI)
24IRQI/OMultiplexed I/O & Peripheral Pin IRQ (General)
25XTAL2I/OMultiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)
26XTAL1I/OMultiplexed I/O & Peripheral Pin XTAL1 (RTC/CLK)
27AVSSGNDGround Reference Pin (AVSS)
28EVDDPowerPower Supply Input (EVDD — 1.8V to 3.6V)
29AVDDPowerPower Supply Input (AVDD — 1.8V to 3.6V)
30AVSSGNDGround Reference Pin (AVSS)
31AVSSGNDGround Reference Pin (AVSS)
32AVSSGNDGround Reference Pin (AVSS)
33EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 DIG3
I/O
Multiplexed I/O & Peripheral Pin DIG3 (General)
Design note: 1 RX/TXIndicator seeSection115 . , . 2 If disabled pull -down enabled (AVSS) . ,
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: AT86RF231-ZU (MICROCHIP · QFN-32-EP(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
AT86RF231-ZU (QFN-32-EP(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT86RF231-ZU (QFN-32-EP(5x5)) - 2. Standard Pinout (Top View)
True package pinout (33 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT86RF231-ZU (QFN-32-EP(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT86RF231-ZU (QFN-32-EP(5x5)) - 4. Package Dimensions (D×E×A)
QFN-32-EP(5x5) · 5.00×5.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT86RF231-ZU (QFN-32-EP(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (33 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT86RF231-ZU (QFN-32-EP(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for AT86RF231
P1 · p01_fig01652×376px
AT86RF231-ZU (QFN-32-EP(5x5)) — Low Power 2.4 GHz Transceiver for ZigBee, IEEE 802.15.4, 6LoWPAN, RF4CE, SP100, WirelessHART, and ISM Applications
Low Power 2.4 GHz Transceiver for ZigBee, IEEE 802.15.4, 6LoWPAN, RF4CE, SP100, WirelessHART, and ISM Applications
P2 · p02_fig01905×955px
AT86RF231-ZU (QFN-32-EP(5x5)) — Figure 1-1. AT86RF231 Pin-out Diagram
Figure 1-1. AT86RF231 Pin-out Diagram
P12 · p12_fig011444×1285px
AT86RF231-ZU (QFN-32-EP(5x5)) — Figure 5-1. Basic Application Schematic
Figure 5-1. Basic Application Schematic
P12 · p12_fig01P12
AT86RF231-ZU (QFN-32-EP(5x5)) — Datasheet Page 12 (p12_fig01)
Datasheet Page 12 (p12_fig01)
P14 · p14_fig011624×1134px
AT86RF231-ZU (QFN-32-EP(5x5)) — Figure 5-2. Extended Feature Application Schematic
Figure 5-2. Extended Feature Application Schematic
P116 · p116_fig011002×786px
AT86RF231-ZU (QFN-32-EP(5x5)) — Figure 9-7. Simplified XOSC Schematic with External Components
Figure 9-7. Simplified XOSC Schematic with External Components
P174 · p174_fig012128×2303px
AT86RF231-ZU (QFN-32-EP(5x5)) — AT86RF231 | 19. Package Drawing - 32QN2 | TITLE DRAWING NO. GPC REV. Package Drawing Contact: packagedrawings@atmel.com 32QN2 ZJZ A 32QN2, 32-lead 5.0 x 5.0 mm Body, 0.50 mm Pitch, Quad Flat No Lead Package (QFN) Sawn | 11/26/07 | COMMON DI
AT86RF231 | 19. Package Drawing - 32QN2 | TITLE DRAWING NO. GPC REV. Package Drawing Contact: packagedrawings@atmel.com 32QN2 ZJZ A 32QN2, 32-lead 5.0 x 5.0 mm Body, 0.50 mm Pitch, Quad Flat No Lead Package (QFN) Sawn | 11/26/07 | COMMON DI
P174 · p174_fig01P174
AT86RF231-ZU (QFN-32-EP(5x5)) — Datasheet Page 174 (p174_fig01)
Datasheet Page 174 (p174_fig01)

Technical Specifications & Part Details (AT86RF231-ZU)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT86RF231-ZU (QFN-32-EP(5x5)) is a 32-pin standard electronic & interconnect component featuring a 5.00 × 5.00 × 0.85 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V to 3.6V supply operation across -40°C to +85°C with integrated SPI, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
2.4 GHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (QFN-32-EP(5x5))
Pin Count & Lead PitchN / e
32 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
SPI, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol33 auto-grouped pins
OK
IPC-7351B Land Pattern33 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 3.30×3.30mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-32-EP(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.50mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
33P / 33Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-32-EP(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT86RF231-ZU (QFN-32-EP(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT86RF231-ZU (QFN-32-EP(5x5))?

Manufactured by MICROCHIP, the AT86RF231-ZU is housed in a QFN-32-EP(5x5) package with 33 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (DIG3: Multiplexed I/O & Peripheral Pin DIG3 (General)), 2 (DIG4: Multiplexed I/O & Peripheral Pin DIG4 (General)), 3 (AVSS: Ground Reference Pin (AVSS)), 4 (RFP: Multiplexed I/O & Peripheral Pin RFP (General)), 5 (RFN: Multiplexed I/O & Peripheral Pin RFN (General)), 6 (AVSS: Ground Reference Pin (AVSS)).

What are the IPC-7351B PCB Footprint dimensions for AT86RF231-ZU?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT86RF231-ZU (QFN-32-EP(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.50 mm, and 33 copper pads plus a central exposed thermal pad (EPAD) of 3.30 × 3.30 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT86RF231-ZU?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT86RF231-ZU (MICROCHIP, QFN-32-EP(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (33 pins) & AT86RF231 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DIG3Digital_IOSignal terminal DIG3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: DIG3. Supported peripheral buses: General.
2DIG4Digital_IOSignal terminal DIG4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: DIG4. Supported peripheral buses: General.
3AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
4RFPRF_50OhmSignal terminal RFP (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RFP. Supported peripheral buses: General.
5RFNRF_50OhmSignal terminal RFN (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RFN. Supported peripheral buses: General.
6AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
7DVSSGND0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
8/RSTDigital_IOSignal terminal /RST (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: /RST. Supported peripheral buses: General.
9DIG1Digital_IOSignal terminal DIG1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: DIG1. Supported peripheral buses: General.
10DIG2Digital_IOSignal terminal DIG2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: DIG2. Supported peripheral buses: General.
11SLP_TRDigital_IOSignal terminal SLP_TR (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SLP_TR. Supported peripheral buses: General.
12DVSSGND0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
13DVDDPower_InPrimary positive power supply input (DVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
14DVDDPower_InPrimary positive power supply input (DVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
15DEVDDPower_InPrimary positive power supply input (DEVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
16DVSSGND0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
17CLKMDigital_IOSignal terminal CLKM (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: CLKM. Supported peripheral buses: General.
18DVSSGND0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
19SCLKDigital_IOSignal terminal SCLK (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SPICLOCK. Supported peripheral buses: SPI, I2C.
20MISODigital_IOSignal terminal MISO (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SPIDATAOUTPUT. Supported peripheral buses: SPI.
21DVSSGND0V electrical ground return terminal (DVSS) for internal core logic, I/O drivers, and analog sub-blocks.
22MOSIDigital_IOSignal terminal MOSI (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SPIDATAINPUT. Supported peripheral buses: SPI.
23/SELDigital_IOSignal terminal /SEL (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: SPISELECT. Supported peripheral buses: SPI.
24IRQDigital_IOSignal terminal IRQ (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: IRQ. Supported peripheral buses: General.
25XTAL2Digital_IOSignal terminal XTAL2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK.
26XTAL1Digital_IOSignal terminal XTAL1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: XTAL1. Supported peripheral buses: RTC/CLK.
27AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
28EVDDPower_InPrimary positive power supply input (EVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
29AVDDPower_InPrimary positive power supply input (AVDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
30AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
31AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
32AVSSGND0V electrical ground return terminal (AVSS) for internal core logic, I/O drivers, and analog sub-blocks.
33EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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