![AT42QT1050-MMH (VQFN-20-EP(3x3)) — 28 AT42QT1050 [PRELIMINARY DATASHEET]](/api/v1/assets/C1522299/extracted/figures/p28_fig01.png)
WLCSP-12(1.4x1.6) · 12P
12P1.6×1.4×0.50mmP=0.4mm
AT42QT1050 (WLCSP-12(1.4x1.6))
Synchronized Pinout (Symbol / 2D / 3D) (21/21)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | Key2 | I/O | Multiplexed I/O & Peripheral Pin Key2 (General) |
| 2 | NotConnected | I/O | Multiplexed I/O & Peripheral Pin NotConnected (General) |
| 3 | Key1 | I/O | Multiplexed I/O & Peripheral Pin Key1 (General) |
| 4 | Key0 | I/O | Multiplexed I/O & Peripheral Pin Key0 (General) |
| 5 | NotConnected | I/O | Multiplexed I/O & Peripheral Pin NotConnected (General) |
| 6 | NotConnected | I/O | Multiplexed I/O & Peripheral Pin NotConnected (General) |
| 7 | NotConnected | I/O | Multiplexed I/O & Peripheral Pin NotConnected (General) |
| 8 | Ground | I/O | Multiplexed I/O & Peripheral Pin Ground (General) |
| 9 | Power | I/O | Multiplexed I/O & Peripheral Pin Power (General) |
| 10 | NotConnected | I/O | Multiplexed I/O & Peripheral Pin NotConnected (General) |
| 11 | IO6 | I/O | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | I2Cdataline | I/O | Multiplexed I/O & Peripheral Pin I2Cdataline (I2C) |
| 13 | IO15 | I/O | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | I/O | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | ConnecttoI2Cclock | I/O | Multiplexed I/O & Peripheral Pin ConnecttoI2Cclock (I2C) |
| 16 | Key4 | I/O | Multiplexed I/O & Peripheral Pin Key4 (General) |
| 17 | Key3 | I/O | Multiplexed I/O & Peripheral Pin Key3 (General) |
| 18 | NotConnected | I/O | Multiplexed I/O & Peripheral Pin NotConnected (General) |
| 19 | NotConnected | I/O | Multiplexed I/O & Peripheral Pin NotConnected (General) |
| 20 | NotConnected | I/O | Multiplexed I/O & Peripheral Pin NotConnected (General) |
| 21 | EPAD | GND | Exposed Thermal & Ground Pad (EPAD) |
PIN 1 Key2
I/OMultiplexed I/O & Peripheral Pin Key2 (General)
Design note: KEY2
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (21 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
VQFN-20-EP(3x3) · 3.00×3.00mm · Pitch 0.45mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (21 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for AT42QT1050
P2 · p02_fig011354×1149px
P2 · p02_fig021472×1068px
P2 · p02_fig02P2
P28 · p28_fig011954×2430px
Technical Specifications & Part Details (AT42QT1050-MMH)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:AT42QT1050-MMH (VQFN-20-EP(3x3)) is a 20-pin standard electronic & interconnect component featuring a 3.00 × 3.00 × 0.85 mm mechanical envelope (lead pitch e = 0.45 mm). Rated for 1.8 V to 5.5 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8 V to 5.5 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
400 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.85 mm (A1=0.03 mm)
Package family: QFN (VQFN-20-EP(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.45 mm (17.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol21 auto-grouped pins
IPC-7351B Land Pattern21 pads · Pitch 0.45mm
IPC-7525 60% Solder PasteEPAD 1.50×1.50mm windowed grid
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — AT42QT1050 (2)
VQFN-20-EP(3x3) · 21P
21P3.0×3.0×0.85mmP=0.45mm
AT42QT1050 (VQFN-20-EP(3x3))
Mechanical Dimensions & Land Pattern (VQFN-20-EP(3x3))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.85mm · e=0.45mm
Pad Size (W × L)Level B
0.28 × 0.80 mm
Pins / Total PadsTopology
21P / 21Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit VQFN-20-EP(3x3) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — AT42QT1050-MMH (VQFN-20-EP(3x3))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of AT42QT1050-MMH (VQFN-20-EP(3x3))?
Manufactured by MICROCHIP, the AT42QT1050-MMH is housed in a VQFN-20-EP(3x3) package with 21 pins and a 0.45 mm lead pitch, supporting a VCC supply range of 1.8 V to 5.5 V. Key pins include: 1 (Key2: Multiplexed I/O & Peripheral Pin Key2 (General)), 2 (NotConnected: Multiplexed I/O & Peripheral Pin NotConnected (General)), 3 (Key1: Multiplexed I/O & Peripheral Pin Key1 (General)), 4 (Key0: Multiplexed I/O & Peripheral Pin Key0 (General)), 5 (NotConnected: Multiplexed I/O & Peripheral Pin NotConnected (General)), 6 (NotConnected: Multiplexed I/O & Peripheral Pin NotConnected (General)).
What are the IPC-7351B PCB Footprint dimensions for AT42QT1050-MMH?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT42QT1050-MMH (VQFN-20-EP(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.45 mm, and 21 copper pads plus a central exposed thermal pad (EPAD) of 1.50 × 1.50 mm with a 60% IPC-7525 windowed solder paste grid.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT42QT1050-MMH?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT42QT1050-MMH (MICROCHIP, VQFN-20-EP(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (21 pins) & AT42QT1050 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | Key2 | Digital_IO | Signal terminal Key2 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key2. Supported peripheral buses: General. |
| 2 | NotConnected | Digital_IO | Signal terminal NotConnected (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: NotConnected. Supported peripheral buses: General. |
| 3 | Key1 | Digital_IO | Signal terminal Key1 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key1. Supported peripheral buses: General. |
| 4 | Key0 | Digital_IO | Signal terminal Key0 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key0. Supported peripheral buses: General. |
| 5 | NotConnected | Digital_IO | Signal terminal NotConnected (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: NotConnected. Supported peripheral buses: General. |
| 6 | NotConnected | Digital_IO | Signal terminal NotConnected (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: NotConnected. Supported peripheral buses: General. |
| 7 | NotConnected | Digital_IO | Signal terminal NotConnected (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: NotConnected. Supported peripheral buses: General. |
| 8 | Ground | Digital_IO | Signal terminal Ground (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Ground. Supported peripheral buses: General. |
| 9 | Power | Digital_IO | Signal terminal Power (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Power. Supported peripheral buses: General. |
| 10 | NotConnected | Digital_IO | Signal terminal NotConnected (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: NotConnected. Supported peripheral buses: General. |
| 11 | IO6 | Digital_IO | GPIO6 / RTC_GPIO6 / TOUCH6 / ADC1_CH5 |
| 12 | I2Cdataline | Digital_IO | Signal terminal I2Cdataline (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: I2Cdataline. Supported peripheral buses: I2C. |
| 13 | IO15 | Digital_IO | GPIO15 / RTC_GPIO15 / U0RTS / ADC2_CH4 / XTAL_32K_P |
| 14 | IO16 | Digital_IO | GPIO16 / RTC_GPIO16 / U0CTS / ADC2_CH5 / XTAL_32K_N |
| 15 | ConnecttoI2Cclock | Digital_IO | Signal terminal ConnecttoI2Cclock (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: ConnecttoI2Cclock. Supported peripheral buses: I2C. |
| 16 | Key4 | Digital_IO | Signal terminal Key4 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key4. Supported peripheral buses: General. |
| 17 | Key3 | Digital_IO | Signal terminal Key3 (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: Key3. Supported peripheral buses: General. |
| 18 | NotConnected | Digital_IO | Signal terminal NotConnected (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: NotConnected. Supported peripheral buses: General. |
| 19 | NotConnected | Digital_IO | Signal terminal NotConnected (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: NotConnected. Supported peripheral buses: General. |
| 20 | NotConnected | Digital_IO | Signal terminal NotConnected (I/O, 1.8 V to 5.5 V domain). Multiplexed alternate functions: NotConnected. Supported peripheral buses: General. |
| 21 | EPAD | GND | Bottom exposed die attach pad (EPAD) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |