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TN0702N3-G (TO-92-3) — Symbol, Footprint IPC-7351B & 3D STEP Model

TN0702N3-G

MICROCHIPID: C152199TO-92-3 · 3 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · TN0702N3-G (TO-92-3)1S2G3DGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.810.25.10-5.1-10.2mm
2. 2D FOOTPRINT
123E=4.90mm · Pitch e=1.27mmD=3.70mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 4.90mm × 3.70mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (3/3)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1SI/OMultiplexed I/O & Peripheral Pin S (General)
2GI/OMultiplexed I/O & Peripheral Pin G (General)
3DI/OMultiplexed I/O & Peripheral Pin D (General)
PIN 1 S
I/O
Multiplexed I/O & Peripheral Pin S (General)
Design note: Signal terminal S (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: TN0702N3-G (MICROCHIP · TO-92-3)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
TN0702N3-G (TO-92-3) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
TN0702N3-G (TO-92-3) - 2. Standard Pinout (Top View)
True package pinout (3 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
TN0702N3-G (TO-92-3) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
TN0702N3-G (TO-92-3) - 4. Package Dimensions (D×E×A)
TO-92-3 · 4.90×3.70mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
TN0702N3-G (TO-92-3) - 5. Recommended Land Pattern
IPC-7351B Footprint (3 Pads)Expand ›
6. Application SchematicSCHEMATIC
TN0702N3-G (TO-92-3) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for TN0702
P1 · p01_fig01EXACT PACKAGE
TN0702N3-G (TO-92-3) — Pin Configuration
Pin Configuration
P5 · p05_fig01EXACT PACKAGE
TN0702N3-G (TO-92-3) — TN0702 | 3-Lead TO-92 Package Outline (N3) | Symbol A b c D E E1 e e1 L | Dimensions | (inches) | MIN .170 .014† .014† .175 .125 .080 .095 .045 .500 | NOM - - - - - - - - - | MAX .210 .022† .022† .205 .165 .105 .105 .055 .610* | JEDEC Regis
TN0702 | 3-Lead TO-92 Package Outline (N3) | Symbol A b c D E E1 e e1 L | Dimensions | (inches) | MIN .170 .014† .014† .175 .125 .080 .095 .045 .500 | NOM - - - - - - - - - | MAX .210 .022† .022† .205 .165 .105 .105 .055 .610* | JEDEC Regis
P1 · p01_fig022034×1022px
TN0702N3-G (TO-92-3) — Pin Configuration
Pin Configuration
P1 · p01_fig02P1
TN0702N3-G (TO-92-3) — Datasheet Page 1 (p01_fig02)
Datasheet Page 1 (p01_fig02)
P2 · p02_fig012034×785px
TN0702N3-G (TO-92-3) — Notes:
Notes:
P3 · p03_fig012038×2777px
TN0702N3-G (TO-92-3) — 3 Supertex inc. | www.supertex.com | Doc.# DSFP-TN0702 C080813 | TN0702 | Typical Performance Curves | Output Characteristics 5.0 | 4.0 | 3.0 | 2.0 | 1.0 | 0 0 5.0 10 15 20 VDS (volts) | Saturation Characteristics | 0 2.0 4.0 6.0 8.0 10 | 3
3 Supertex inc. | www.supertex.com | Doc.# DSFP-TN0702 C080813 | TN0702 | Typical Performance Curves | Output Characteristics 5.0 | 4.0 | 3.0 | 2.0 | 1.0 | 0 0 5.0 10 15 20 VDS (volts) | Saturation Characteristics | 0 2.0 4.0 6.0 8.0 10 | 3
P5 · p05_fig01P5
TN0702N3-G (TO-92-3) — Datasheet Page 5 (p05_fig01)
Datasheet Page 5 (p05_fig01)

Technical Specifications & Part Details (TN0702N3-G)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:TN0702N3-G (TO-92-3) is a 3-pin standard electronic & interconnect component featuring a 4.90 × 3.70 × 4.60 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated Standard I/O / Passive interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1.0MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.70 × 4.60 mm (A1=1.50 mm)
Package family: TO92 (TO-92-3)
Pin Count & Lead PitchN / e
3 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
Standard I/O / Passive
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol3 auto-grouped pins
OK
IPC-7351B Land Pattern3 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TO-92-3)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.90 × 3.70 mm
Height (A) & Pitch (e)IPC-7351B
A=4.60mm · e=1.27mm
Pad Size (W × L)Level B
0.95 × 1.55 mm
Pins / Total PadsTopology
3P / 3Pad (THT_TO92)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TO-92-3
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — TN0702N3-G (TO-92-3)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of TN0702N3-G (TO-92-3)?

Manufactured by MICROCHIP, the TN0702N3-G is housed in a TO-92-3 package with 3 pins and a 1.27 mm lead pitch. Key pins include: 1 (S: Multiplexed I/O & Peripheral Pin S (General)), 2 (G: Multiplexed I/O & Peripheral Pin G (General)), 3 (D: Multiplexed I/O & Peripheral Pin D (General)).

What are the IPC-7351B PCB Footprint dimensions for TN0702N3-G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), TN0702N3-G (TO-92-3) has a nominal body envelope of 3.70 × 4.90 mm, pitch e = 1.27 mm, and 3 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for TN0702N3-G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for TN0702N3-G (MICROCHIP, TO-92-3) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (3 pins) & TN0702 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1SDigital_IOSignal terminal S (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: S. Supported peripheral buses: General.
2GDigital_IOSignal terminal G (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: G. Supported peripheral buses: General.
3DDigital_IOSignal terminal D (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D. Supported peripheral buses: General.
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