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CH559L (LQFP-48(7x7)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH559L

WCHID: C150548LQFP-48(7x7) · 48 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH559L (LQFP-48(7x7))1P1.6/AIN6/MI2P1.7/AIN7/SC3P5.7/RST4P3.0/RXD5P4.5/PWM2_/A6IO37P3.1/TXD8P3.2/LED0/IN9P3.3/LED1/!A10P3.4/LEDC/XC11P3.5/DA6/T112P3.6/WR13P3.7/RD14P4.3/PWM1_/A15P4.2/PWM3_/C16P4.6/XI/SCS_17P4.7/XO/SCK_18GND19P4.1/A120P4.0/LED2/A021P2.0/A822P2.1/MOSI1/A23P2.2/MISO1/A24P2.3/SCK1/A148P1.5/AIN5/MO47P1.4/AIN4/SC46P1.3/AIN345P1.2/AIN2/PW44P1.1/AIN1/T243P1.0/AIN0/T242VDD3341VIN540P00 .39P01 .38P02 .37P03 .36P04 .35P05 .34P06 .33P07 .32P5.0/DM31P5.1/DP30P5.4/HM/ALE/29P5.5/HP/!A1528P2.7/TXD1/DA27P2.6/RXD1/A126IO2125P2.4/PWM1/A1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.235.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748E=7.00mm · Pitch e=0.50mmD=7.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (48/48)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P1.6/AIN6/MISOI/OMultiplexed I/O & Peripheral Pin P1.6/AIN6/MISO (SPI, ADC)
2P1.7/AIN7/SCKI/OMultiplexed I/O & Peripheral Pin P1.7/AIN7/SCK (SPI, ADC)
3P5.7/RSTI/OMultiplexed I/O & Peripheral Pin P5.7/RST (General)
4P3.0/RXDI/OMultiplexed I/O & Peripheral Pin P3.0/RXD (UART)
5P4.5/PWM2_/A5I/OMultiplexed I/O & Peripheral Pin P4.5/PWM2_/A5 (PWM)
6IO3I/OGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7P3.1/TXDI/OMultiplexed I/O & Peripheral Pin P3.1/TXD (UART)
8P3.2/LED0/INT0I/OMultiplexed I/O & Peripheral Pin P3.2/LED0/INT0 (General)
9P3.3/LED1/!A15/INT1I/OMultiplexed I/O & Peripheral Pin P3.3/LED1/!A15/INT1 (General)
10P3.4/LEDC/XCS0/T0I/OMultiplexed I/O & Peripheral Pin P3.4/LEDC/XCS0/T0 (General)
11P3.5/DA6/T1I/OMultiplexed I/O & Peripheral Pin P3.5/DA6/T1 (General)
12P3.6/WRI/OMultiplexed I/O & Peripheral Pin P3.6/WR (General)
13P3.7/RDI/OMultiplexed I/O & Peripheral Pin P3.7/RD (General)
14P4.3/PWM1_/A3I/OMultiplexed I/O & Peripheral Pin P4.3/PWM1_/A3 (PWM)
15P4.2/PWM3_/CAP3_/A2I/OMultiplexed I/O & Peripheral Pin P4.2/PWM3_/CAP3_/A2 (PWM)
16P4.6/XI/SCS_I/OMultiplexed I/O & Peripheral Pin P4.6/XI/SCS_ (RTC/CLK)
17P4.7/XO/SCK_I/OMultiplexed I/O & Peripheral Pin P4.7/XO/SCK_ (SPI, RTC/CLK)
18GNDGNDGround Reference Pin (GND)
19P4.1/A1I/OMultiplexed I/O & Peripheral Pin P4.1/A1 (General)
20P4.0/LED2/A0/RXD1_I/OMultiplexed I/O & Peripheral Pin P4.0/LED2/A0/RXD1_ (UART)
21P2.0/A8I/OMultiplexed I/O & Peripheral Pin P2.0/A8 (General)
22P2.1/MOSI1/A9I/OMultiplexed I/O & Peripheral Pin P2.1/MOSI1/A9 (SPI)
23P2.2/MISO1/A10I/OMultiplexed I/O & Peripheral Pin P2.2/MISO1/A10 (SPI)
24P2.3/SCK1/A11I/OMultiplexed I/O & Peripheral Pin P2.3/SCK1/A11 (SPI)
25P2.4/PWM1/A12I/OMultiplexed I/O & Peripheral Pin P2.4/PWM1/A12 (PWM)
26IO21I/OGPIO21 / RTC_GPIO21
27P2.6/RXD1/A14I/OMultiplexed I/O & Peripheral Pin P2.6/RXD1/A14 (UART)
28P2.7/TXD1/DA7/A15I/OMultiplexed I/O & Peripheral Pin P2.7/TXD1/DA7/A15 (UART)
29P5.5/HP/!A15/XAI/OMultiplexed I/O & Peripheral Pin P5.5/HP/!A15/XA (General)
30P5.4/HM/ALE/XBI/OMultiplexed I/O & Peripheral Pin P5.4/HM/ALE/XB (General)
31P5.1/DPI/OMultiplexed I/O & Peripheral Pin P5.1/DP (General)
32P5.0/DMI/OMultiplexed I/O & Peripheral Pin P5.0/DM (General)
33P07 .I/OMultiplexed I/O & Peripheral Pin P07 . (General)
34P06 .I/OMultiplexed I/O & Peripheral Pin P06 . (General)
35P05 .I/OMultiplexed I/O & Peripheral Pin P05 . (General)
36P04 .I/OMultiplexed I/O & Peripheral Pin P04 . (General)
37P03 .I/OMultiplexed I/O & Peripheral Pin P03 . (UART)
38P02 .I/OMultiplexed I/O & Peripheral Pin P02 . (UART)
39P01 .I/OMultiplexed I/O & Peripheral Pin P01 . (General)
40P00 .I/OMultiplexed I/O & Peripheral Pin P00 . (CAN)
41VIN5PowerPower Supply Input (VIN5 — 5V to 3.3V)
42VDD33PowerRegulated Power Output (VDD33 — 5V to 3.3V)
43P1.0/AIN0/T2/CAP1I/OMultiplexed I/O & Peripheral Pin P1.0/AIN0/T2/CAP1 (ADC)
44P1.1/AIN1/T2EX/CAP2I/OMultiplexed I/O & Peripheral Pin P1.1/AIN1/T2EX/CAP2 (ADC)
45P1.2/AIN2/PWM3/CAP3I/OMultiplexed I/O & Peripheral Pin P1.2/AIN2/PWM3/CAP3 (ADC, PWM)
46P1.3/AIN3I/OMultiplexed I/O & Peripheral Pin P1.3/AIN3 (ADC)
47P1.4/AIN4/SCSI/OMultiplexed I/O & Peripheral Pin P1.4/AIN4/SCS (ADC)
48P1.5/AIN5/MOSII/OMultiplexed I/O & Peripheral Pin P1.5/AIN5/MOSI (SPI, ADC)
PIN 1 P1.6/AIN6/MISO
I/O
Multiplexed I/O & Peripheral Pin P1.6/AIN6/MISO (SPI, ADC)
Design note: Signal terminal P1.6/AIN6/MISO (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.6/AIN6/MISO. Supported peripheral buses: SPI, ADC.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH559L (WCH · LQFP-48(7x7))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH559L (LQFP-48(7x7)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH559L (LQFP-48(7x7)) - 2. Standard Pinout (Top View)
True package pinout (48 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH559L (LQFP-48(7x7)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH559L (LQFP-48(7x7)) - 4. Package Dimensions (D×E×A)
LQFP-48(7x7) · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH559L (LQFP-48(7x7)) - 5. Recommended Land Pattern
IPC-7351B Footprint (48 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH559L (LQFP-48(7x7)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for CH559
P1 · p01_fig011745×914px
CH559L (LQFP-48(7x7)) — Here is CH559 internal block diagram, for reference only.
Here is CH559 internal block diagram, for reference only.
P3 · p03_fig011736×980px
CH559L (LQFP-48(7x7)) — Package Body size Lead pitch Description Part No.
Package Body size Lead pitch Description Part No.
P3 · p03_fig01P3
CH559L (LQFP-48(7x7)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P91 · p91_fig011790×1236px
CH559L (LQFP-48(7x7)) — CH559 Datasheet 91 http://wch.cn
CH559 Datasheet 91 http://wch.cn

Technical Specifications & Part Details (CH559L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH559L (LQFP-48(7x7)) is a 48-pin standard electronic & interconnect component featuring a 7.00 × 7.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 5V to 3.3V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM, CAN, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
5V to 3.3V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
56MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-48(7x7))
Pin Count & Lead PitchN / e
48 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM, CAN, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol48 auto-grouped pins
OK
IPC-7351B Land Pattern48 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — CH559 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (LQFP-48(7x7))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
48P / 48Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-48(7x7)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH559L (LQFP-48(7x7))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH559L (LQFP-48(7x7))?

Manufactured by WCH, the CH559L is housed in a LQFP-48(7x7) package with 48 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 5V to 3.3V. Key pins include: 1 (P1.6/AIN6/MISO: Multiplexed I/O & Peripheral Pin P1.6/AIN6/MISO (SPI, ADC)), 2 (P1.7/AIN7/SCK: Multiplexed I/O & Peripheral Pin P1.7/AIN7/SCK (SPI, ADC)), 3 (P5.7/RST: Multiplexed I/O & Peripheral Pin P5.7/RST (General)), 4 (P3.0/RXD: Multiplexed I/O & Peripheral Pin P3.0/RXD (UART)), 5 (P4.5/PWM2_/A5: Multiplexed I/O & Peripheral Pin P4.5/PWM2_/A5 (PWM)), 6 (IO3: GPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)).

What are the IPC-7351B PCB Footprint dimensions for CH559L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH559L (LQFP-48(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 48 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH559L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH559L (WCH, LQFP-48(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (48 pins) & CH559 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P1.6/AIN6/MISODigital_IOSignal terminal P1.6/AIN6/MISO (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.6/AIN6/MISO. Supported peripheral buses: SPI, ADC.
2P1.7/AIN7/SCKDigital_IOSignal terminal P1.7/AIN7/SCK (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.7/AIN7/SCK. Supported peripheral buses: SPI, ADC.
3P5.7/RSTDigital_IOSignal terminal P5.7/RST (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P5.7/RST. Supported peripheral buses: General.
4P3.0/RXDDigital_IOSignal terminal P3.0/RXD (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.0/RXD. Supported peripheral buses: UART.
5P4.5/PWM2_/A5Digital_IOSignal terminal P4.5/PWM2_/A5 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P4.5/PWM2_/A5. Supported peripheral buses: PWM.
6IO3Digital_IOGPIO3 / RTC_GPIO3 / TOUCH3 / ADC1_CH2 (JTAG Source Strap)
7P3.1/TXDDigital_IOSignal terminal P3.1/TXD (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.1/TXD. Supported peripheral buses: UART.
8P3.2/LED0/INT0Digital_IOSignal terminal P3.2/LED0/INT0 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.2/LED0/INT0. Supported peripheral buses: General.
9P3.3/LED1/!A15/INT1Digital_IOSignal terminal P3.3/LED1/!A15/INT1 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.3/LED1/!A15/INT1. Supported peripheral buses: General.
10P3.4/LEDC/XCS0/T0Digital_IOSignal terminal P3.4/LEDC/XCS0/T0 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.4/LEDC/XCS0/T0. Supported peripheral buses: General.
11P3.5/DA6/T1Digital_IOSignal terminal P3.5/DA6/T1 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.5/DA6/T1. Supported peripheral buses: General.
12P3.6/WRDigital_IOSignal terminal P3.6/WR (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.6/WR. Supported peripheral buses: General.
13P3.7/RDDigital_IOSignal terminal P3.7/RD (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P3.7/RD. Supported peripheral buses: General.
14P4.3/PWM1_/A3Digital_IOSignal terminal P4.3/PWM1_/A3 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P4.3/PWM1_/A3. Supported peripheral buses: PWM.
15P4.2/PWM3_/CAP3_/A2Digital_IOSignal terminal P4.2/PWM3_/CAP3_/A2 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P4.2/PWM3_/CAP3_/A2. Supported peripheral buses: PWM.
16P4.6/XI/SCS_Digital_IOSignal terminal P4.6/XI/SCS_ (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P4.6/XI/SCS_. Supported peripheral buses: RTC/CLK.
17P4.7/XO/SCK_Digital_IOSignal terminal P4.7/XO/SCK_ (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P4.7/XO/SCK_. Supported peripheral buses: SPI, RTC/CLK.
18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
19P4.1/A1Digital_IOSignal terminal P4.1/A1 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P4.1/A1. Supported peripheral buses: General.
20P4.0/LED2/A0/RXD1_Digital_IOSignal terminal P4.0/LED2/A0/RXD1_ (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P4.0/LED2/A0/RXD1_. Supported peripheral buses: UART.
21P2.0/A8Digital_IOSignal terminal P2.0/A8 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P2.0/A8. Supported peripheral buses: General.
22P2.1/MOSI1/A9Digital_IOSignal terminal P2.1/MOSI1/A9 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P2.1/MOSI1/A9. Supported peripheral buses: SPI.
23P2.2/MISO1/A10Digital_IOSignal terminal P2.2/MISO1/A10 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P2.2/MISO1/A10. Supported peripheral buses: SPI.
24P2.3/SCK1/A11Digital_IOSignal terminal P2.3/SCK1/A11 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P2.3/SCK1/A11. Supported peripheral buses: SPI.
25P2.4/PWM1/A12Digital_IOSignal terminal P2.4/PWM1/A12 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P2.4/PWM1/A12. Supported peripheral buses: PWM.
26IO21Digital_IOGPIO21 / RTC_GPIO21
27P2.6/RXD1/A14Digital_IOSignal terminal P2.6/RXD1/A14 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P2.6/RXD1/A14. Supported peripheral buses: UART.
28P2.7/TXD1/DA7/A15Digital_IOSignal terminal P2.7/TXD1/DA7/A15 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P2.7/TXD1/DA7/A15. Supported peripheral buses: UART.
29P5.5/HP/!A15/XADigital_IOSignal terminal P5.5/HP/!A15/XA (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P5.5/HP/!A15/XA. Supported peripheral buses: General.
30P5.4/HM/ALE/XBDigital_IOSignal terminal P5.4/HM/ALE/XB (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P5.4/HM/ALE/XB. Supported peripheral buses: General.
31P5.1/DPDigital_IOSignal terminal P5.1/DP (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P5.1/DP. Supported peripheral buses: General.
32P5.0/DMDigital_IOSignal terminal P5.0/DM (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P5.0/DM. Supported peripheral buses: General.
33P07 .Digital_IOSignal terminal P07 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P07 .. Supported peripheral buses: General.
34P06 .Digital_IOSignal terminal P06 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P06 .. Supported peripheral buses: General.
35P05 .Digital_IOSignal terminal P05 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P05 .. Supported peripheral buses: General.
36P04 .Digital_IOSignal terminal P04 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P04 .. Supported peripheral buses: General.
37P03 .Digital_IOSignal terminal P03 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P03 .. Supported peripheral buses: UART.
38P02 .Digital_IOSignal terminal P02 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P02 .. Supported peripheral buses: UART.
39P01 .Digital_IOSignal terminal P01 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P01 .. Supported peripheral buses: General.
40P00 .Open_DrainSignal terminal P00 . (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P00 .. Supported peripheral buses: CAN.
41VIN5Power_InPrimary positive power supply input (VIN5) operating in the 5V to 3.3V domain (Max rating: 5.0V).
42VDD33Power_OutRegulated power output rail (VDD33) operating in the 5V to 3.3V domain (Max rating: 5.0V).
43P1.0/AIN0/T2/CAP1AnalogSignal terminal P1.0/AIN0/T2/CAP1 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.0/AIN0/T2/CAP1. Supported peripheral buses: ADC.
44P1.1/AIN1/T2EX/CAP2AnalogSignal terminal P1.1/AIN1/T2EX/CAP2 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.1/AIN1/T2EX/CAP2. Supported peripheral buses: ADC.
45P1.2/AIN2/PWM3/CAP3AnalogSignal terminal P1.2/AIN2/PWM3/CAP3 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.2/AIN2/PWM3/CAP3. Supported peripheral buses: ADC, PWM.
46P1.3/AIN3AnalogSignal terminal P1.3/AIN3 (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.3/AIN3. Supported peripheral buses: ADC.
47P1.4/AIN4/SCSAnalogSignal terminal P1.4/AIN4/SCS (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.4/AIN4/SCS. Supported peripheral buses: ADC.
48P1.5/AIN5/MOSIDigital_IOSignal terminal P1.5/AIN5/MOSI (I/O, 5V to 3.3V domain). Multiplexed alternate functions: P1.5/AIN5/MOSI. Supported peripheral buses: SPI, ADC.
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