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PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC16LF15356T-I/ML

MICROCHIPQFN-28-EP(6x6) · 29 Pins · Pitch 0.50mmDISCREPANCY REVIEW REQUIRED5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC16LF15356T-I/ML (QFN-28-EP(6x6))1RA22RA33RA44RA55VSS6RA77RA68RC09RC110RC211RC312RC413RC514RC615RC729EP28RA127RA026RE3/MCLR/VPP25RB7/ICSPDAT24RB6/ICSPCLK23RB522RB421RB320RB219RB118RB017VDD16VSSGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.825.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829E=6.00mm · Pitch e=0.50mmD=6.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 6.00mm × 6.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (29/29)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1RA2I/OMultiplexed I/O & Peripheral Pin RA2 (General)
2RA3I/OMultiplexed I/O & Peripheral Pin RA3 (General)
3RA4I/OMultiplexed I/O & Peripheral Pin RA4 (General)
4RA5I/OMultiplexed I/O & Peripheral Pin RA5 (General)
5VSSGNDGround Reference Pin (VSS)
6RA7I/OMultiplexed I/O & Peripheral Pin RA7 (General)
7RA6I/OMultiplexed I/O & Peripheral Pin RA6 (General)
8RC0I/OMultiplexed I/O & Peripheral Pin RC0 (General)
9RC1I/OMultiplexed I/O & Peripheral Pin RC1 (General)
10RC2I/OMultiplexed I/O & Peripheral Pin RC2 (General)
11RC3I/OMultiplexed I/O & Peripheral Pin RC3 (General)
12RC4I/OMultiplexed I/O & Peripheral Pin RC4 (General)
13RC5I/OMultiplexed I/O & Peripheral Pin RC5 (General)
14RC6I/OMultiplexed I/O & Peripheral Pin RC6 (General)
15RC7I/OMultiplexed I/O & Peripheral Pin RC7 (General)
16VSSGNDGround Reference Pin (VSS)
17VDDPowerPower Supply Input (VDD — 1.8V to 3.6V)
18RB0I/OMultiplexed I/O & Peripheral Pin RB0 (General)
19RB1I/OMultiplexed I/O & Peripheral Pin RB1 (General)
20RB2I/OMultiplexed I/O & Peripheral Pin RB2 (General)
21RB3I/OMultiplexed I/O & Peripheral Pin RB3 (General)
22RB4I/OMultiplexed I/O & Peripheral Pin RB4 (General)
23RB5I/OMultiplexed I/O & Peripheral Pin RB5 (General)
24RB6/ICSPCLKI/OMultiplexed I/O & Peripheral Pin RB6/ICSPCLK (General)
25RB7/ICSPDATI/OMultiplexed I/O & Peripheral Pin RB7/ICSPDAT (General)
26RE3/MCLR/VPPI/OMultiplexed I/O & Peripheral Pin RE3/MCLR/VPP (General)
27RA0I/OMultiplexed I/O & Peripheral Pin RA0 (General)
28RA1I/OMultiplexed I/O & Peripheral Pin RA1 (General)
29EPGNDExposed Thermal & Ground Pad (EP)
PIN 1 RA2
I/O
Multiplexed I/O & Peripheral Pin RA2 (General)
Design note: Signal terminal RA2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
1. Realistic 3D PackageREPRESENTATIVE
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) - 2. Standard Pinout (Top View)
True package pinout (29 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) - 4. Package Dimensions (D×E×A)
QFN-28-EP(6x6) · 6.00×6.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) - 5. Recommended Land Pattern
IPC-7351B Footprint (29 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for PIC16LF15356 / PIC16LF15386
P43 · p43_fig011777×1127px
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS
FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS
P166 · p166_fig011777×950px
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — FIGURE 11-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT
FIGURE 11-2: WAKE-UP FROM SLEEP THROUGH INTERRUPT
P362 · p362_fig01867×407px
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — FIGURE 28-3: CCP PWM OUTPUT SIGNAL
FIGURE 28-3: CCP PWM OUTPUT SIGNAL
P430 · p430_fig01867×588px
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — FIGURE 32-11: I2C MASTER/ SLAVE CONNECTION
FIGURE 32-11: I2C MASTER/ SLAVE CONNECTION
P504 · p504_fig011778×844px
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — FIGURE 35-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
FIGURE 35-2: PICkit™ PROGRAMMER STYLE CONNECTOR INTERFACE
P504 · p504_fig021778×1133px
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — FIGURE 35-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
FIGURE 35-3: TYPICAL CONNECTION FOR ICSP™ PROGRAMMING
P504 · p504_fig02P504
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — Datasheet Page 504 (p504_fig02)
Datasheet Page 504 (p504_fig02)
P572 · p572_fig011778×2506px
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — PIC16(L)F15356/75/76/85/86
PIC16(L)F15356/75/76/85/86
P574 · p574_fig011778×2493px
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) —  2016 Microchip Technology Inc. Preliminary DS40001866A-page 574 | Microchip Technology Drawing C04-103D Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip
 2016 Microchip Technology Inc. Preliminary DS40001866A-page 574 | Microchip Technology Drawing C04-103D Sheet 2 of 2 | For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip
P574 · p574_fig01P574
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — Datasheet Page 574 (p574_fig01)
Datasheet Page 574 (p574_fig01)
P575 · p575_fig011778×2500px
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) —  2016 Microchip Technology Inc. Preliminary DS40001866A-page 575 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Contact Pad Spacing | Optional Center Pad Length | Contact Pitch | Y2 X2 | 6.60 6.60
 2016 Microchip Technology Inc. Preliminary DS40001866A-page 575 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Contact Pad Spacing | Optional Center Pad Length | Contact Pitch | Y2 X2 | 6.60 6.60
P575 · p575_fig01P575
PIC16LF15356T-I/ML (QFN-28-EP(6x6)) — Datasheet Page 575 (p575_fig01)
Datasheet Page 575 (p575_fig01)
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (PIC16LF15356T-I/ML)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC16LF15356T-I/ML (QFN-28-EP(6x6)) is a 28-pin standard electronic & interconnect component featuring a 6.00 × 6.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V to 3.6V supply operation across -40°C to 85°C with integrated UART, SPI, I2C, ADC, DAC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
6.00 × 6.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-28-EP(6x6))
Pin Count & Lead PitchN / e
28 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, DAC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol29 auto-grouped pins
OK
IPC-7351B Land Pattern29 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 6.60×6.60mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — PIC16LF15356 / PIC16LF15386 (2)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (QFN-28-EP(6x6))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
6.00 × 6.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.35 × 0.85 mm
Pins / Total PadsTopology
29P / 29Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-28-EP(6x6)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC16LF15356T-I/ML (QFN-28-EP(6x6))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC16LF15356T-I/ML (QFN-28-EP(6x6))?

Manufactured by MICROCHIP, the PIC16LF15356T-I/ML is housed in a QFN-28-EP(6x6) package with 29 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.8V to 3.6V. Key pins include: 1 (RA2: Multiplexed I/O & Peripheral Pin RA2 (General)), 2 (RA3: Multiplexed I/O & Peripheral Pin RA3 (General)), 3 (RA4: Multiplexed I/O & Peripheral Pin RA4 (General)), 4 (RA5: Multiplexed I/O & Peripheral Pin RA5 (General)), 5 (VSS: Ground Reference Pin (VSS)), 6 (RA7: Multiplexed I/O & Peripheral Pin RA7 (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC16LF15356T-I/ML?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC16LF15356T-I/ML (QFN-28-EP(6x6)) has a nominal body envelope of 6.00 × 6.00 mm, pitch e = 0.50 mm, and 29 copper pads plus a central exposed thermal pad (EPAD) of 6.60 × 6.60 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC16LF15356T-I/ML?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC16LF15356T-I/ML (MICROCHIP, QFN-28-EP(6x6)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (29 pins) & PIC16LF15356 / PIC16LF15386 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1RA2Digital_IOSignal terminal RA2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA2. Supported peripheral buses: General.
2RA3Digital_IOSignal terminal RA3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA3. Supported peripheral buses: General.
3RA4Digital_IOSignal terminal RA4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA4. Supported peripheral buses: General.
4RA5Digital_IOSignal terminal RA5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA5. Supported peripheral buses: General.
5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
6RA7Digital_IOSignal terminal RA7 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA7. Supported peripheral buses: General.
7RA6Digital_IOSignal terminal RA6 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA6. Supported peripheral buses: General.
8RC0Digital_IOSignal terminal RC0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC0. Supported peripheral buses: General.
9RC1Digital_IOSignal terminal RC1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC1. Supported peripheral buses: General.
10RC2Digital_IOSignal terminal RC2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC2. Supported peripheral buses: General.
11RC3Digital_IOSignal terminal RC3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC3. Supported peripheral buses: General.
12RC4Digital_IOSignal terminal RC4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC4. Supported peripheral buses: General.
13RC5Digital_IOSignal terminal RC5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC5. Supported peripheral buses: General.
14RC6Digital_IOSignal terminal RC6 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC6. Supported peripheral buses: General.
15RC7Digital_IOSignal terminal RC7 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RC7. Supported peripheral buses: General.
16VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
17VDDPower_InPrimary positive power supply input (VDD) operating in the 1.8V to 3.6V domain (Max rating: 3.6V).
18RB0Digital_IOSignal terminal RB0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB0. Supported peripheral buses: General.
19RB1Digital_IOSignal terminal RB1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB1. Supported peripheral buses: General.
20RB2Digital_IOSignal terminal RB2 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB2. Supported peripheral buses: General.
21RB3Digital_IOSignal terminal RB3 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB3. Supported peripheral buses: General.
22RB4Digital_IOSignal terminal RB4 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB4. Supported peripheral buses: General.
23RB5Digital_IOSignal terminal RB5 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB5. Supported peripheral buses: General.
24RB6/ICSPCLKDigital_IOSignal terminal RB6/ICSPCLK (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB6/ICSPCLK. Supported peripheral buses: General.
25RB7/ICSPDATDigital_IOSignal terminal RB7/ICSPDAT (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RB7/ICSPDAT. Supported peripheral buses: General.
26RE3/MCLR/VPPDigital_IOSignal terminal RE3/MCLR/VPP (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RE3/MCLR/VPP. Supported peripheral buses: General.
27RA0Digital_IOSignal terminal RA0 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA0. Supported peripheral buses: General.
28RA1Digital_IOSignal terminal RA1 (I/O, 1.8V to 3.6V domain). Multiplexed alternate functions: RA1. Supported peripheral buses: General.
29EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
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