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AT89C51RB2-3CSUL (PDIL-40) — Symbol, Footprint IPC-7351B & 3D STEP Model

AT89C51RB2-3CSUL

MICROCHIPPDIL-40 · 40 Pins · Pitch 2.54mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · AT89C51RB2-3CSUL (PDIL-40)1P1.0/T22P1.1/T2EX/SS3P1.2/ECI4P1.3CEX05P1.4/CEX16P1.5/CEX2/MI7P1.6/CEX3/SC8P1.7CEX4/MOS9IO410P3.0/RxD11P3.1/TxD12P3.2/INT0#13P3.3/INT1#14P3.4/T015P3.5/T116P3.6/WR#17P3.7/RD#18IO1919IO2020VSS40VCC39P0.0/AD038P0.1/AD137P0.2/AD236P0.3/AD335P0.4/AD434P0.5/AD533P0.6/AD632P0.7/AD731IO3130IO3029IO2928P2.7/A1527P2.6/A1426P2.5/A1325P2.4/A1224P2.3/A1123P2.2/A1022P2.1/A921P2.0/A8Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.830.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940E=13.90mm · Pitch e=2.54mmD=50.26mm-22-20-18-16-14-12-10-8-6-4-2024681012141618202239373533312927252321191715131197531-1-3-5-7-9-11-13-15-17-19-21-23-25-27-29-31-33-35-37-39mm
3. 3D CAD MODEL
Package Body: 13.90mm × 50.26mm · Pitch: 2.54mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (40/40)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1P1.0/T2I/OMultiplexed I/O & Peripheral Pin P1.0/T2 (General)
2P1.1/T2EX/SSI/OMultiplexed I/O & Peripheral Pin P1.1/T2EX/SS (General)
3P1.2/ECII/OMultiplexed I/O & Peripheral Pin P1.2/ECI (General)
4P1.3CEX0I/OMultiplexed I/O & Peripheral Pin P1.3CEX0 (General)
5P1.4/CEX1I/OMultiplexed I/O & Peripheral Pin P1.4/CEX1 (General)
6P1.5/CEX2/MISOI/OMultiplexed I/O & Peripheral Pin P1.5/CEX2/MISO (SPI)
7P1.6/CEX3/SCKI/OMultiplexed I/O & Peripheral Pin P1.6/CEX3/SCK (SPI)
8P1.7CEX4/MOSII/OMultiplexed I/O & Peripheral Pin P1.7CEX4/MOSI (SPI)
9IO4I/OGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10P3.0/RxDI/OMultiplexed I/O & Peripheral Pin P3.0/RxD (UART)
11P3.1/TxDI/OMultiplexed I/O & Peripheral Pin P3.1/TxD (UART)
12P3.2/INT0#I/OMultiplexed I/O & Peripheral Pin P3.2/INT0# (General)
13P3.3/INT1#I/OMultiplexed I/O & Peripheral Pin P3.3/INT1# (General)
14P3.4/T0I/OMultiplexed I/O & Peripheral Pin P3.4/T0 (General)
15P3.5/T1I/OMultiplexed I/O & Peripheral Pin P3.5/T1 (General)
16P3.6/WR#I/OMultiplexed I/O & Peripheral Pin P3.6/WR# (General)
17P3.7/RD#I/OMultiplexed I/O & Peripheral Pin P3.7/RD# (General)
18IO19I/OGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20VSSGNDGround Reference Pin (VSS)
21P2.0/A8I/OMultiplexed I/O & Peripheral Pin P2.0/A8 (General)
22P2.1/A9I/OMultiplexed I/O & Peripheral Pin P2.1/A9 (General)
23P2.2/A10I/OMultiplexed I/O & Peripheral Pin P2.2/A10 (General)
24P2.3/A11I/OMultiplexed I/O & Peripheral Pin P2.3/A11 (General)
25P2.4/A12I/OMultiplexed I/O & Peripheral Pin P2.4/A12 (General)
26P2.5/A13I/OMultiplexed I/O & Peripheral Pin P2.5/A13 (General)
27P2.6/A14I/OMultiplexed I/O & Peripheral Pin P2.6/A14 (General)
28P2.7/A15I/OMultiplexed I/O & Peripheral Pin P2.7/A15 (General)
29IO29I/OGeneral Purpose Digital I/O Pin IO29
30IO30I/OGeneral Purpose Digital I/O Pin IO30
31IO31I/OGeneral Purpose Digital I/O Pin IO31
32P0.7/AD7I/OMultiplexed I/O & Peripheral Pin P0.7/AD7 (General)
33P0.6/AD6I/OMultiplexed I/O & Peripheral Pin P0.6/AD6 (General)
34P0.5/AD5I/OMultiplexed I/O & Peripheral Pin P0.5/AD5 (General)
35P0.4/AD4I/OMultiplexed I/O & Peripheral Pin P0.4/AD4 (General)
36P0.3/AD3I/OMultiplexed I/O & Peripheral Pin P0.3/AD3 (General)
37P0.2/AD2I/OMultiplexed I/O & Peripheral Pin P0.2/AD2 (General)
38P0.1/AD1I/OMultiplexed I/O & Peripheral Pin P0.1/AD1 (General)
39P0.0/AD0I/OMultiplexed I/O & Peripheral Pin P0.0/AD0 (General)
40VCCPowerPower Supply Input (VCC — 2.7V to 5.5V)
PIN 1 P1.0/T2
I/O
Multiplexed I/O & Peripheral Pin P1.0/T2 (General)
Design note: Signal terminal P1.0/T2 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1.0/T2. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
1. Realistic 3D PackageREPRESENTATIVE
AT89C51RB2-3CSUL (PDIL-40) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
AT89C51RB2-3CSUL (PDIL-40) - 2. Standard Pinout (Top View)
True package pinout (40 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
AT89C51RB2-3CSUL (PDIL-40) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
AT89C51RB2-3CSUL (PDIL-40) - 4. Package Dimensions (D×E×A)
PDIL-40 · 13.90×50.26mm · Pitch 2.54mmExpand ›
5. Recommended Land PatternLAND PATTERN
AT89C51RB2-3CSUL (PDIL-40) - 5. Recommended Land Pattern
IPC-7351B Footprint (40 Pads)Expand ›
6. Application SchematicSCHEMATIC
AT89C51RB2-3CSUL (PDIL-40) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for AT89C51RB2
P1 · p01_fig01624×502px
AT89C51RB2-3CSUL (PDIL-40) — 40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only) - In X2 mode (6 Clocks/machine cycle)
40 MHz (Vcc 2.7V to 5.5V, both Internal and external code execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only) - In X2 mode (6 Clocks/machine cycle)
P9 · p09_fig01765×871px
AT89C51RB2-3CSUL (PDIL-40) — Figure 2. Pin Configurations
Figure 2. Pin Configurations
P9 · p09_fig02977×863px
AT89C51RB2-3CSUL (PDIL-40) — Figure 2. Pin Configurations
Figure 2. Pin Configurations
P9 · p09_fig03991×905px
AT89C51RB2-3CSUL (PDIL-40) — 43 42 41 40 39 44 38 37 36 35 34 | P1.4/CEX1 | P1.0/T2 | P1.1/T2EX/SS | P1.3/CEX0 | P1.2/ECI | NIC* | VCC | P0.0/AD0 | P0.2/AD2 | P0.3/AD3 | P0.1/AD1 | P0.4/AD4 | P0.6/AD6 | P0.5/AD5 | P0.7/AD7 | ALE/PROG | PSEN | EA | NIC* | P2.7/A15 | P2.
43 42 41 40 39 44 38 37 36 35 34 | P1.4/CEX1 | P1.0/T2 | P1.1/T2EX/SS | P1.3/CEX0 | P1.2/ECI | NIC* | VCC | P0.0/AD0 | P0.2/AD2 | P0.3/AD3 | P0.1/AD1 | P0.4/AD4 | P0.6/AD6 | P0.5/AD5 | P0.7/AD7 | ALE/PROG | PSEN | EA | NIC* | P2.7/A15 | P2.
P9 · p09_fig01P9
AT89C51RB2-3CSUL (PDIL-40) — Datasheet Page 9 (p09_fig01)
Datasheet Page 9 (p09_fig01)
P10 · p10_fig011508×2373px
AT89C51RB2-3CSUL (PDIL-40) — 10 AT89C51RB2/RC2
10 AT89C51RB2/RC2
P10 · p10_fig01P10
AT89C51RB2-3CSUL (PDIL-40) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)
P120 · p120_fig011257×1653px
AT89C51RB2-3CSUL (PDIL-40) — Package Information
Package Information

Technical Specifications & Part Details (AT89C51RB2-3CSUL)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:AT89C51RB2-3CSUL (PDIL-40) is a 40-pin standard electronic & interconnect component featuring a 50.26 × 13.90 × 4.20 mm mechanical envelope (lead pitch e = 2.54 mm). Rated for 2.7V to 5.5V supply operation across -40°C to +85°C with integrated UART, SPI interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
50.26 × 13.90 × 4.20 mm (A1=0.51 mm)
Package family: DIP (PDIL-40)
Pin Count & Lead PitchN / e
40 Pins | Pitch e = 2.54 mm (100.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol40 auto-grouped pins
OK
IPC-7351B Land Pattern40 pads · Pitch 2.54mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (PDIL-40)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
50.26 × 13.90 mm
Height (A) & Pitch (e)IPC-7351B
A=4.20mm · e=2.54mm
Pad Size (W × L)Level B
1.60 × 1.60 mm
Pins / Total PadsTopology
40P / 40Pad (THT_DIP)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
PDIL-40
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — AT89C51RB2-3CSUL (PDIL-40)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of AT89C51RB2-3CSUL (PDIL-40)?

Manufactured by MICROCHIP, the AT89C51RB2-3CSUL is housed in a PDIL-40 package with 40 pins and a 2.54 mm lead pitch, supporting a VCC supply range of 2.7V to 5.5V. Key pins include: 1 (P1.0/T2: Multiplexed I/O & Peripheral Pin P1.0/T2 (General)), 2 (P1.1/T2EX/SS: Multiplexed I/O & Peripheral Pin P1.1/T2EX/SS (General)), 3 (P1.2/ECI: Multiplexed I/O & Peripheral Pin P1.2/ECI (General)), 4 (P1.3CEX0: Multiplexed I/O & Peripheral Pin P1.3CEX0 (General)), 5 (P1.4/CEX1: Multiplexed I/O & Peripheral Pin P1.4/CEX1 (General)), 6 (P1.5/CEX2/MISO: Multiplexed I/O & Peripheral Pin P1.5/CEX2/MISO (SPI)).

What are the IPC-7351B PCB Footprint dimensions for AT89C51RB2-3CSUL?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), AT89C51RB2-3CSUL (PDIL-40) has a nominal body envelope of 13.90 × 50.26 mm, pitch e = 2.54 mm, and 40 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for AT89C51RB2-3CSUL?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for AT89C51RB2-3CSUL (MICROCHIP, PDIL-40) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (40 pins) & AT89C51RB2 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1P1.0/T2Digital_IOSignal terminal P1.0/T2 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1.0/T2. Supported peripheral buses: General.
2P1.1/T2EX/SSDigital_IOSignal terminal P1.1/T2EX/SS (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1.1/T2EX/SS. Supported peripheral buses: General.
3P1.2/ECIDigital_IOSignal terminal P1.2/ECI (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1.2/ECI. Supported peripheral buses: General.
4P1.3CEX0Digital_IOSignal terminal P1.3CEX0 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1.3CEX0. Supported peripheral buses: General.
5P1.4/CEX1Digital_IOSignal terminal P1.4/CEX1 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1.4/CEX1. Supported peripheral buses: General.
6P1.5/CEX2/MISODigital_IOSignal terminal P1.5/CEX2/MISO (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1.5/CEX2/MISO. Supported peripheral buses: SPI.
7P1.6/CEX3/SCKDigital_IOSignal terminal P1.6/CEX3/SCK (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1.6/CEX3/SCK. Supported peripheral buses: SPI.
8P1.7CEX4/MOSIDigital_IOSignal terminal P1.7CEX4/MOSI (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P1.7CEX4/MOSI. Supported peripheral buses: SPI.
9IO4Digital_IOGPIO4 / RTC_GPIO4 / TOUCH4 / ADC1_CH3
10P3.0/RxDDigital_IOSignal terminal P3.0/RxD (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3.0/RxD. Supported peripheral buses: UART.
11P3.1/TxDDigital_IOSignal terminal P3.1/TxD (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3.1/TxD. Supported peripheral buses: UART.
12P3.2/INT0#Digital_IOSignal terminal P3.2/INT0# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3.2/INT0#. Supported peripheral buses: General.
13P3.3/INT1#Digital_IOSignal terminal P3.3/INT1# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3.3/INT1#. Supported peripheral buses: General.
14P3.4/T0Digital_IOSignal terminal P3.4/T0 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3.4/T0. Supported peripheral buses: General.
15P3.5/T1Digital_IOSignal terminal P3.5/T1 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3.5/T1. Supported peripheral buses: General.
16P3.6/WR#Digital_IOSignal terminal P3.6/WR# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3.6/WR#. Supported peripheral buses: General.
17P3.7/RD#Digital_IOSignal terminal P3.7/RD# (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P3.7/RD#. Supported peripheral buses: General.
18IO19Digital_IOGPIO19 / RTC_GPIO19 / USB_D- / U1RTS / ADC2_CH8
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
21P2.0/A8Digital_IOSignal terminal P2.0/A8 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2.0/A8. Supported peripheral buses: General.
22P2.1/A9Digital_IOSignal terminal P2.1/A9 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2.1/A9. Supported peripheral buses: General.
23P2.2/A10Digital_IOSignal terminal P2.2/A10 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2.2/A10. Supported peripheral buses: General.
24P2.3/A11Digital_IOSignal terminal P2.3/A11 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2.3/A11. Supported peripheral buses: General.
25P2.4/A12Digital_IOSignal terminal P2.4/A12 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2.4/A12. Supported peripheral buses: General.
26P2.5/A13Digital_IOSignal terminal P2.5/A13 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2.5/A13. Supported peripheral buses: General.
27P2.6/A14Digital_IOSignal terminal P2.6/A14 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2.6/A14. Supported peripheral buses: General.
28P2.7/A15Digital_IOSignal terminal P2.7/A15 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P2.7/A15. Supported peripheral buses: General.
29IO29Digital_IOGeneral Purpose Digital I/O Pin IO29
30IO30Digital_IOGeneral Purpose Digital I/O Pin IO30
31IO31Digital_IOGeneral Purpose Digital I/O Pin IO31
32P0.7/AD7Digital_IOSignal terminal P0.7/AD7 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0.7/AD7. Supported peripheral buses: General.
33P0.6/AD6Digital_IOSignal terminal P0.6/AD6 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0.6/AD6. Supported peripheral buses: General.
34P0.5/AD5Digital_IOSignal terminal P0.5/AD5 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0.5/AD5. Supported peripheral buses: General.
35P0.4/AD4Digital_IOSignal terminal P0.4/AD4 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0.4/AD4. Supported peripheral buses: General.
36P0.3/AD3Digital_IOSignal terminal P0.3/AD3 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0.3/AD3. Supported peripheral buses: General.
37P0.2/AD2Digital_IOSignal terminal P0.2/AD2 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0.2/AD2. Supported peripheral buses: General.
38P0.1/AD1Digital_IOSignal terminal P0.1/AD1 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0.1/AD1. Supported peripheral buses: General.
39P0.0/AD0Digital_IOSignal terminal P0.0/AD0 (I/O, 2.7V to 5.5V domain). Multiplexed alternate functions: P0.0/AD0. Supported peripheral buses: General.
40VCCPower_InPrimary positive power supply input (VCC) operating in the 2.7V to 5.5V domain (Max rating: 5.5V).
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