![ATMEGA169PA-MCH (QFN-64(7x7)) — 30 ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]](/api/v1/assets/C1340586/extracted/figures/p30_fig01.png)
![ATMEGA169PA-MCH (QFN-64(7x7)) — 31 ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]](/api/v1/assets/C1340586/extracted/figures/p31_fig01.png)
![ATMEGA169PA-MCH (QFN-64(7x7)) — 32 ATmega169A/PA/329A/PA/649A/P/3290A/PA/6490A/P [DATASHEET SUMMARY]](/api/v1/assets/C1340586/extracted/figures/p32_fig01.png)
QFN-64(7x7) · 65P
65P7.0×7.0×1.35mmP=0.65mm
ATMEGA169PA (QFN-64(7x7))
Synchronized Pinout (Symbol / 2D / 3D) (65/65)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 65 | EP | GND | Exposed Thermal & Ground Pad (EP) |
| A1 | PE0 | I/O | Multiplexed I/O & Peripheral Pin PE0 (General) |
| A2 | PE1 | I/O | Multiplexed I/O & Peripheral Pin PE1 (General) |
| A3 | PE3 | I/O | Multiplexed I/O & Peripheral Pin PE3 (General) |
| A4 | PE5 | I/O | Multiplexed I/O & Peripheral Pin PE5 (General) |
| A5 | PE7 | I/O | Multiplexed I/O & Peripheral Pin PE7 (General) |
| A6 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (General) |
| A7 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (General) |
| A8 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| A9 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| A10 | PG3 | I/O | Multiplexed I/O & Peripheral Pin PG3 (General) |
| A11 | RESET# | I | System Enable & Hardware Reset (RESET#) |
| A12 | GND | GND | Ground Reference Pin (GND) |
| A13 | XTAL1(TOSC1) | I/O | Multiplexed I/O & Peripheral Pin XTAL1(TOSC1) (RTC/CLK) |
| A14 | PD1(SEG21) | I/O | Multiplexed I/O & Peripheral Pin PD1(SEG21) (General) |
| A15 | PD3(SEG19) | I/O | Multiplexed I/O & Peripheral Pin PD3(SEG19) (General) |
| A16 | PD5(SEG17) | I/O | Multiplexed I/O & Peripheral Pin PD5(SEG17) (General) |
| A17 | PD6(SEG16) | I/O | Multiplexed I/O & Peripheral Pin PD6(SEG16) (General) |
| A18 | PG1(SEG13) | I/O | Multiplexed I/O & Peripheral Pin PG1(SEG13) (General) |
| A19 | PC0(SEG12) | I/O | Multiplexed I/O & Peripheral Pin PC0(SEG12) (General) |
| A20 | PC2(SEG10) | I/O | Multiplexed I/O & Peripheral Pin PC2(SEG10) (General) |
| A21 | PC4(SEG8) | I/O | Multiplexed I/O & Peripheral Pin PC4(SEG8) (General) |
| A22 | PC6(SEG6) | I/O | Multiplexed I/O & Peripheral Pin PC6(SEG6) (General) |
| A23 | PG2(SEG4) | I/O | Multiplexed I/O & Peripheral Pin PG2(SEG4) (General) |
| A24 | PA6(SEG2) | I/O | Multiplexed I/O & Peripheral Pin PA6(SEG2) (General) |
| A25 | PA5(SEG1) | I/O | Multiplexed I/O & Peripheral Pin PA5(SEG1) (General) |
| A26 | PA2(COM2) | I/O | Multiplexed I/O & Peripheral Pin PA2(COM2) (General) |
| A27 | PA1(COM1) | I/O | Multiplexed I/O & Peripheral Pin PA1(COM1) (General) |
| A28 | VCC | Power | Power Supply Input (VCC — 1.8V ~ 5.5V VCC) |
| A29 | PF7 | I/O | Multiplexed I/O & Peripheral Pin PF7 (General) |
| A30 | PF5 | I/O | Multiplexed I/O & Peripheral Pin PF5 (General) |
| A31 | PF3 | I/O | Multiplexed I/O & Peripheral Pin PF3 (General) |
| A32 | PF1 | I/O | Multiplexed I/O & Peripheral Pin PF1 (General) |
| A33 | AREF | I/O | Multiplexed I/O & Peripheral Pin AREF (ADC) |
| A34 | GND | GND | Ground Reference Pin (GND) |
| B1 | VLCDCAP | I/O | Multiplexed I/O & Peripheral Pin VLCDCAP (General) |
| B2 | PE2 | I/O | Multiplexed I/O & Peripheral Pin PE2 (General) |
| B3 | PE4 | I/O | Multiplexed I/O & Peripheral Pin PE4 (General) |
| B4 | PE6 | I/O | Multiplexed I/O & Peripheral Pin PE6 (General) |
| B5 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (General) |
| B6 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (General) |
| B7 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| B8 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (General) |
| B9 | PG4 | I/O | Multiplexed I/O & Peripheral Pin PG4 (General) |
| B10 | VCC | Power | Power Supply Input (VCC — 1.8V ~ 5.5V VCC) |
| B11 | XTAL2(TOSC2) | I/O | Multiplexed I/O & Peripheral Pin XTAL2(TOSC2) (RTC/CLK) |
| B12 | PD0(SEG22) | I/O | Multiplexed I/O & Peripheral Pin PD0(SEG22) (General) |
| B13 | PD2(SEG20) | I/O | Multiplexed I/O & Peripheral Pin PD2(SEG20) (General) |
| B14 | PD4(SEG18) | I/O | Multiplexed I/O & Peripheral Pin PD4(SEG18) (General) |
| B15 | PD7(SEG15) | I/O | Multiplexed I/O & Peripheral Pin PD7(SEG15) (General) |
| B16 | PG0(SEG14) | I/O | Multiplexed I/O & Peripheral Pin PG0(SEG14) (General) |
| B17 | PC1(SEG11) | I/O | Multiplexed I/O & Peripheral Pin PC1(SEG11) (General) |
| B18 | PC3(SEG9) | I/O | Multiplexed I/O & Peripheral Pin PC3(SEG9) (General) |
| B19 | PC5(SEG7) | I/O | Multiplexed I/O & Peripheral Pin PC5(SEG7) (General) |
| B20 | PC7(SEG5) | I/O | Multiplexed I/O & Peripheral Pin PC7(SEG5) (General) |
| B21 | PA7(SEG3) | I/O | Multiplexed I/O & Peripheral Pin PA7(SEG3) (General) |
| B22 | PA4(SEG0) | I/O | Multiplexed I/O & Peripheral Pin PA4(SEG0) (General) |
| B23 | PA3(COM3) | I/O | Multiplexed I/O & Peripheral Pin PA3(COM3) (General) |
| B24 | PA0(COM0) | I/O | Multiplexed I/O & Peripheral Pin PA0(COM0) (General) |
| B25 | GND | GND | Ground Reference Pin (GND) |
| B26 | PF6 | I/O | Multiplexed I/O & Peripheral Pin PF6 (General) |
| B27 | PF4 | I/O | Multiplexed I/O & Peripheral Pin PF4 (General) |
| B28 | PF2 | I/O | Multiplexed I/O & Peripheral Pin PF2 (General) |
| B29 | PF0 | I/O | Multiplexed I/O & Peripheral Pin PF0 (General) |
| B30 | AVCC | Power | Power Supply Input (AVCC — 1.8V ~ 5.5V VCC) |
PIN 65 EP
GNDExposed Thermal & Ground Pad (EP)
Design note: Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (65 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-64(7x7) · 7.00×7.00mm · Pitch 0.65mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (65 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for ATMEGA169PA
P5 · p05_fig01EXACT PACKAGE
P3 · p03_fig011994×1996px
P4 · p04_fig011946×2052px
P4 · p04_fig01P4
P5 · p05_fig01P5
P30 · p30_fig012035×2372px
P31 · p31_fig012027×2252px
P32 · p32_fig012033×2250px
Technical Specifications & Part Details (ATMEGA169PA-MCH)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:ATMEGA169PA-MCH (QFN-64(7x7)) is a 65-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 1.35 mm mechanical envelope (lead pitch e = 0.65 mm). Rated for 1.8V ~ 5.5V supply operation across -40°C to 85°C with integrated UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
65 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (QFN-64(7x7))
Pin Count & Lead PitchN / e
65 Pins | Pitch e = 0.65 mm (25.6 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, JTAG / SWD, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol65 auto-grouped pins
IPC-7351B Land Pattern65 pads · Pitch 0.65mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — ATMEGA169PA (2)
QFN-64(7x7) · 65P
65P7.0×7.0×1.35mmP=0.65mm
ATMEGA169PA (QFN-64(7x7))
Mechanical Dimensions & Land Pattern (QFN-64(7x7))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.65mm
Pad Size (W × L)Level B
0.25 × 0.25 mm
Pins / Total PadsTopology
65P / 65Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-64(7x7) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — ATMEGA169PA-MCH (QFN-64(7x7))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ATMEGA169PA-MCH (QFN-64(7x7))?
Manufactured by MICROCHIP, the ATMEGA169PA-MCH is housed in a QFN-64(7x7) package with 65 pins and a 0.65 mm lead pitch. Key pins include: 65 (EP: Exposed Thermal & Ground Pad (EP)), A1 (PE0: Multiplexed I/O & Peripheral Pin PE0 (General)), A2 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A3 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), A5 (PE7: Multiplexed I/O & Peripheral Pin PE7 (General)).
What are the IPC-7351B PCB Footprint dimensions for ATMEGA169PA-MCH?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATMEGA169PA-MCH (QFN-64(7x7)) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.65 mm, and 65 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATMEGA169PA-MCH?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATMEGA169PA-MCH (MICROCHIP, QFN-64(7x7)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (65 pins) & ATMEGA169PA Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 65 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |
| A1 | PE0 | Digital_IO | Signal terminal PE0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General. |
| A2 | PE1 | Digital_IO | Signal terminal PE1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General. |
| A3 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| A4 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General. |
| A5 | PE7 | Digital_IO | Signal terminal PE7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General. |
| A6 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General. |
| A7 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General. |
| A8 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| A9 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General. |
| A10 | PG3 | Digital_IO | Signal terminal PG3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PG3. Supported peripheral buses: General. |
| A11 | RESET# | Digital_IO | Active-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals. |
| A12 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| A13 | XTAL1(TOSC1) | Digital_IO | Signal terminal XTAL1(TOSC1) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL1(TOSC1). Supported peripheral buses: RTC/CLK. |
| A14 | PD1(SEG21) | Digital_IO | Signal terminal PD1(SEG21) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD1(SEG21). Supported peripheral buses: General. |
| A15 | PD3(SEG19) | Digital_IO | Signal terminal PD3(SEG19) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD3(SEG19). Supported peripheral buses: General. |
| A16 | PD5(SEG17) | Digital_IO | Signal terminal PD5(SEG17) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD5(SEG17). Supported peripheral buses: General. |
| A17 | PD6(SEG16) | Digital_IO | Signal terminal PD6(SEG16) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD6(SEG16). Supported peripheral buses: General. |
| A18 | PG1(SEG13) | Digital_IO | Signal terminal PG1(SEG13) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PG1(SEG13). Supported peripheral buses: General. |
| A19 | PC0(SEG12) | Digital_IO | Signal terminal PC0(SEG12) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC0(SEG12). Supported peripheral buses: General. |
| A20 | PC2(SEG10) | Digital_IO | Signal terminal PC2(SEG10) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC2(SEG10). Supported peripheral buses: General. |
| A21 | PC4(SEG8) | Digital_IO | Signal terminal PC4(SEG8) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC4(SEG8). Supported peripheral buses: General. |
| A22 | PC6(SEG6) | Digital_IO | Signal terminal PC6(SEG6) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC6(SEG6). Supported peripheral buses: General. |
| A23 | PG2(SEG4) | Digital_IO | Signal terminal PG2(SEG4) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PG2(SEG4). Supported peripheral buses: General. |
| A24 | PA6(SEG2) | Digital_IO | Signal terminal PA6(SEG2) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA6(SEG2). Supported peripheral buses: General. |
| A25 | PA5(SEG1) | Digital_IO | Signal terminal PA5(SEG1) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA5(SEG1). Supported peripheral buses: General. |
| A26 | PA2(COM2) | Digital_IO | Signal terminal PA2(COM2) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA2(COM2). Supported peripheral buses: General. |
| A27 | PA1(COM1) | Digital_IO | Signal terminal PA1(COM1) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA1(COM1). Supported peripheral buses: General. |
| A28 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V). |
| A29 | PF7 | Digital_IO | Signal terminal PF7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PF7. Supported peripheral buses: General. |
| A30 | PF5 | Digital_IO | Signal terminal PF5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General. |
| A31 | PF3 | Digital_IO | Signal terminal PF3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General. |
| A32 | PF1 | Digital_IO | Signal terminal PF1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General. |
| A33 | AREF | Digital_IO | Signal terminal AREF (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: AREF. Supported peripheral buses: ADC. |
| A34 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| B1 | VLCDCAP | Digital_IO | Signal terminal VLCDCAP (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: VLCDCAP. Supported peripheral buses: General. |
| B2 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General. |
| B3 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General. |
| B4 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General. |
| B5 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General. |
| B6 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General. |
| B7 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General. |
| B8 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General. |
| B9 | PG4 | Digital_IO | Signal terminal PG4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PG4. Supported peripheral buses: General. |
| B10 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V). |
| B11 | XTAL2(TOSC2) | Digital_IO | Signal terminal XTAL2(TOSC2) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL2(TOSC2). Supported peripheral buses: RTC/CLK. |
| B12 | PD0(SEG22) | Digital_IO | Signal terminal PD0(SEG22) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD0(SEG22). Supported peripheral buses: General. |
| B13 | PD2(SEG20) | Digital_IO | Signal terminal PD2(SEG20) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD2(SEG20). Supported peripheral buses: General. |
| B14 | PD4(SEG18) | Digital_IO | Signal terminal PD4(SEG18) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD4(SEG18). Supported peripheral buses: General. |
| B15 | PD7(SEG15) | Digital_IO | Signal terminal PD7(SEG15) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD7(SEG15). Supported peripheral buses: General. |
| B16 | PG0(SEG14) | Digital_IO | Signal terminal PG0(SEG14) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PG0(SEG14). Supported peripheral buses: General. |
| B17 | PC1(SEG11) | Digital_IO | Signal terminal PC1(SEG11) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC1(SEG11). Supported peripheral buses: General. |
| B18 | PC3(SEG9) | Digital_IO | Signal terminal PC3(SEG9) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC3(SEG9). Supported peripheral buses: General. |
| B19 | PC5(SEG7) | Digital_IO | Signal terminal PC5(SEG7) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC5(SEG7). Supported peripheral buses: General. |
| B20 | PC7(SEG5) | Digital_IO | Signal terminal PC7(SEG5) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC7(SEG5). Supported peripheral buses: General. |
| B21 | PA7(SEG3) | Digital_IO | Signal terminal PA7(SEG3) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA7(SEG3). Supported peripheral buses: General. |
| B22 | PA4(SEG0) | Digital_IO | Signal terminal PA4(SEG0) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA4(SEG0). Supported peripheral buses: General. |
| B23 | PA3(COM3) | Digital_IO | Signal terminal PA3(COM3) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA3(COM3). Supported peripheral buses: General. |
| B24 | PA0(COM0) | Digital_IO | Signal terminal PA0(COM0) (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA0(COM0). Supported peripheral buses: General. |
| B25 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| B26 | PF6 | Digital_IO | Signal terminal PF6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PF6. Supported peripheral buses: General. |
| B27 | PF4 | Digital_IO | Signal terminal PF4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General. |
| B28 | PF2 | Digital_IO | Signal terminal PF2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General. |
| B29 | PF0 | Digital_IO | Signal terminal PF0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General. |