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STM32L011F4U3TR (UFQFPN-20(3x3)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32L011F4U3TR

STID: C1339306UFQFPN-20(3x3) · 20 Pins · Pitch 0.45mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32L011F4U3TR (UFQFPN-20(3x3))1PC14 - OSC322PC15 - OSC323NRST4VDDA5PA0CK IN -_6PA17PA48PA59PA610PA720PB9 BOOT0 -19PB718PB617PA1416PA1315PA1014PA913VDD12VSS11PB1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.817.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
4789121314171819201610235615111E=3.00mm · Pitch e=0.45mmD=3.00mm-3-2-101233210-1-2-3mm
3. 3D CAD MODEL
Package Body: 3.00mm × 3.00mm · Pitch: 0.45mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (20/20)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1PC14 - OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
2PC15 - OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)
3NRSTISystem Enable & Hardware Reset (NRST)
4VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
5PA0CK IN -_I/OMultiplexed I/O & Peripheral Pin PA0CK IN -_ (UART, ADC, PWM, RTC/CLK)
6PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, I2C, ADC, PWM)
7PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, I2C, ADC)
8PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, PWM)
9PA6I/OMultiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC)
10PA7I/OMultiplexed I/O & Peripheral Pin PA7 (UART, SPI, ADC)
11PB1I/OMultiplexed I/O & Peripheral Pin PB1 (UART, SPI, ADC)
12VSSGNDGround Reference Pin (VSS)
13VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
14PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C, RTC/CLK)
15PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART, I2C, PWM, RTC/CLK)
16PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SPI, I2C, SWD/JTAG)
17PA14I/OMultiplexed I/O & Peripheral Pin PA14 (UART, SPI, I2C, SWD/JTAG)
18PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C, PWM)
19PB7I/OMultiplexed I/O & Peripheral Pin PB7 (UART, I2C, PWM)
20PB9 BOOT0 -I/OMultiplexed I/O & Peripheral Pin PB9 BOOT0 - (General)
PIN 1 PC14 - OSC32_IN
I/O
Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)
Design note: Add: OSC32_IN
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 15 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32L011F4U3TR (ST · UFQFPN-20(3x3))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32L011F4U3TR (UFQFPN-20(3x3)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32L011F4U3TR (UFQFPN-20(3x3)) - 2. Standard Pinout (Top View)
True package pinout (20 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32L011F4U3TR (UFQFPN-20(3x3)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32L011F4U3TR (UFQFPN-20(3x3)) - 4. Package Dimensions (D×E×A)
UFQFPN-20(3x3) · 3.00×3.00mm · Pitch 0.45mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32L011F4U3TR (UFQFPN-20(3x3)) - 5. Recommended Land Pattern
IPC-7351B Footprint (20 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32L011F4U3TR (UFQFPN-20(3x3)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (15 figures · Page 1/2)
Showing 1–12 of 15 uncropped original figures for STM32L011
P1 · p01_fig01EXACT PACKAGE
STM32L011F4U3TR (UFQFPN-20(3x3)) — • 4x peripherals communication interface
• 4x peripherals communication interface
P35 · p35_fig01EXACT PACKAGE
STM32L011F4U3TR (UFQFPN-20(3x3)) — Figure 7. STM32L011x3/4 UFQFPN20 pinout
Figure 7. STM32L011x3/4 UFQFPN20 pinout
P106 · p106_fig01EXACT PACKAGE
STM32L011F4U3TR (UFQFPN-20(3x3)) — Figure 44. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Figure 44. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
P107 · p107_fig01EXACT PACKAGE
STM32L011F4U3TR (UFQFPN-20(3x3)) — Figure 45. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Figure 45. UFQFPN20 - 20-lead, 3x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
P35 · p35_fig021546×972px
STM32L011F4U3TR (UFQFPN-20(3x3)) — Figure 8. STM32L011x3/4 TSSOP20 pinout
Figure 8. STM32L011x3/4 TSSOP20 pinout
P35 · p35_fig01P35
STM32L011F4U3TR (UFQFPN-20(3x3)) — Datasheet Page 35 (p35_fig01)
Datasheet Page 35 (p35_fig01)
P36 · p36_fig011548×682px
STM32L011F4U3TR (UFQFPN-20(3x3)) — Figure 9. STM32L011x3/4 TSSOP14 pinout
Figure 9. STM32L011x3/4 TSSOP14 pinout
P45 · p45_fig011555×1257px
STM32L011F4U3TR (UFQFPN-20(3x3)) — Figure 12. Power supply scheme
Figure 12. Power supply scheme
P45 · p45_fig021546×586px
STM32L011F4U3TR (UFQFPN-20(3x3)) — Figure 13. Current consumption measurement scheme
Figure 13. Current consumption measurement scheme
P45 · p45_fig01P45
STM32L011F4U3TR (UFQFPN-20(3x3)) — Datasheet Page 45 (p45_fig01)
Datasheet Page 45 (p45_fig01)
P84 · p84_fig011546×705px
STM32L011F4U3TR (UFQFPN-20(3x3)) — Figure 28. Typical connection diagram using the ADC
Figure 28. Typical connection diagram using the ADC
P84 · p84_fig021752×1045px
STM32L011F4U3TR (UFQFPN-20(3x3)) — 2. Measured at VDD = 3 V ±10 mV. V30 ADC conversion result is stored in the TS_CAL1 byte.
2. Measured at VDD = 3 V ±10 mV. V30 ADC conversion result is stored in the TS_CAL1 byte.
Page 1 / 2 (15 extracted figures)

Technical Specifications & Part Details (STM32L011F4U3TR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32L011F4U3TR (UFQFPN-20(3x3)) is a 20-pin embedded microcontroller unit (mcu) featuring a 3.00 × 3.00 × 0.55 mm mechanical envelope (lead pitch e = 0.45 mm). Rated for 1.65 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.65 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 kHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
11 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
3.00 × 3.00 × 0.55 mm (A1=0.04 mm)
Package family: QFN (UFQFPN-20(3x3))
Pin Count & Lead PitchN / e
20 Pins | Pitch e = 0.45 mm (17.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB9 BOOT0 -): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol20 auto-grouped pins
OK
IPC-7351B Land Pattern20 pads · Pitch 0.45mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (UFQFPN-20(3x3))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
3.00 × 3.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.55mm · e=0.45mm
Pad Size (W × L)Level B
0.30 × 0.70 mm
Pins / Total PadsTopology
20P / 20Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFQFPN-20(3x3)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32L011F4U3TR (UFQFPN-20(3x3))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32L011F4U3TR (UFQFPN-20(3x3))?

Manufactured by ST, the STM32L011F4U3TR is housed in a UFQFPN-20(3x3) package with 20 pins and a 0.45 mm lead pitch, supporting a VCC supply range of 1.65 V to 3.6 V. Key pins include: 1 (PC14 - OSC32_IN: Multiplexed I/O & Peripheral Pin PC14 - OSC32_IN (RTC/CLK)), 2 (PC15 - OSC32_OUT: Multiplexed I/O & Peripheral Pin PC15 - OSC32_OUT (RTC/CLK)), 3 (NRST: System Enable & Hardware Reset (NRST)), 4 (VDDA: Power Supply Input (VDDA — 3.3V VDD (Max 4.0V))), 5 (PA0CK IN -_: Multiplexed I/O & Peripheral Pin PA0CK IN -_ (UART, ADC, PWM, RTC/CLK)), 6 (PA1: Multiplexed I/O & Peripheral Pin PA1 (UART, I2C, ADC, PWM)).

What are the IPC-7351B PCB Footprint dimensions for STM32L011F4U3TR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L011F4U3TR (UFQFPN-20(3x3)) has a nominal body envelope of 3.00 × 3.00 mm, pitch e = 0.45 mm, and 20 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L011F4U3TR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L011F4U3TR (ST, UFQFPN-20(3x3)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (20 pins) & STM32L011 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1PC14 - OSC32_INDigital_IOSignal terminal PC14 - OSC32_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC32_IN. Supported peripheral buses: RTC/CLK.
2PC15 - OSC32_OUTDigital_IOSignal terminal PC15 - OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32_OUT. Supported peripheral buses: RTC/CLK.
3NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
4VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
5PA0CK IN -_Digital_IOSignal terminal PA0CK IN -_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0CK IN -_. Supported peripheral buses: UART, ADC, PWM, RTC/CLK.
6PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA. Supported peripheral buses: UART, I2C, ADC, PWM.
7PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS, I2C1_SCL. Supported peripheral buses: UART, SPI, I2C, ADC.
8PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, PWM.
9PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC.
10PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, ADC.
11PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: UART, SPI, ADC.
12VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
14PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, RTC/CLK.
15PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C, PWM, RTC/CLK.
16PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA, SPI1_SCK. Supported peripheral buses: SPI, I2C, SWD/JTAG.
17PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG.
18PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, PWM.
19PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: UART, I2C, PWM.
20PB9 BOOT0 -Digital_IOSignal terminal PB9 BOOT0 - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9 BOOT0 -. Supported peripheral buses: General.
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