QFN-44(5x5) · 45P
45P5.0×5.0×1.35mmP=0.53mm
ATMEGA164PA / ATMEGA324A / ATMEGA324PA (QFN-44(5x5))
Synchronized Pinout (Symbol / 2D / 3D) (45/45)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 45 | EP | GND | Exposed Thermal & Ground Pad (EP) |
| A1 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| A2 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| A3 | VCC | Power | Power Supply Input (VCC — 1.8V ~ 5.5V VCC) |
| A4 | XTAL2 | I/O | Multiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK) |
| A5 | PD0 | I/O | Multiplexed I/O & Peripheral Pin PD0 (General) |
| A6 | PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 (General) |
| A7 | PD3 | I/O | Multiplexed I/O & Peripheral Pin PD3 (General) |
| A8 | PD5 | I/O | Multiplexed I/O & Peripheral Pin PD5 (General) |
| A9 | PD7 | I/O | Multiplexed I/O & Peripheral Pin PD7 (General) |
| A10 | GND | GND | Ground Reference Pin (GND) |
| A11 | PC1 | I/O | Multiplexed I/O & Peripheral Pin PC1 (General) |
| A12 | PC3 | I/O | Multiplexed I/O & Peripheral Pin PC3 (General) |
| A13 | PC4 | I/O | Multiplexed I/O & Peripheral Pin PC4 (General) |
| A14 | PC6 | I/O | Multiplexed I/O & Peripheral Pin PC6 (General) |
| A15 | AVCC | Power | Power Supply Input (AVCC — 1.8V ~ 5.5V VCC) |
| A16 | AREF | I/O | Multiplexed I/O & Peripheral Pin AREF (ADC) |
| A17 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (General) |
| A18 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (General) |
| A19 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (General) |
| A20 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (General) |
| A21 | VCC | Power | Power Supply Input (VCC — 1.8V ~ 5.5V VCC) |
| A22 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (General) |
| A23 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (General) |
| A24 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| B1 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (General) |
| B2 | RESET# | I | System Enable & Hardware Reset (RESET#) |
| B3 | GND | GND | Ground Reference Pin (GND) |
| B4 | XTAL1 | I/O | Multiplexed I/O & Peripheral Pin XTAL1 (RTC/CLK) |
| B5 | PD1 | I/O | Multiplexed I/O & Peripheral Pin PD1 (General) |
| B6 | PD4 | I/O | Multiplexed I/O & Peripheral Pin PD4 (General) |
| B7 | PD6 | I/O | Multiplexed I/O & Peripheral Pin PD6 (General) |
| B8 | VCC | Power | Power Supply Input (VCC — 1.8V ~ 5.5V VCC) |
| B9 | PC0 | I/O | Multiplexed I/O & Peripheral Pin PC0 (General) |
| B10 | PC2 | I/O | Multiplexed I/O & Peripheral Pin PC2 (General) |
| B11 | PC5 | I/O | Multiplexed I/O & Peripheral Pin PC5 (General) |
| B12 | PC7 | I/O | Multiplexed I/O & Peripheral Pin PC7 (General) |
| B13 | GND | GND | Ground Reference Pin (GND) |
| B14 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (General) |
| B15 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (General) |
| B16 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (General) |
| B17 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (General) |
| B18 | GND | GND | Ground Reference Pin (GND) |
| B19 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (General) |
| B20 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (General) |
PIN 45 EP
GNDExposed Thermal & Ground Pad (EP)
Design note: Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (45 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
QFN-44(5x5) · 5.00×5.00mm · Pitch 0.53mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (45 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for ATMEGA164PA / ATMEGA324A / ATMEGA324PA
P1 · p01_fig01376×200px
P12 · p12_fig011418×890px
P12 · p12_fig01P12
P13 · p13_fig011628×995px
P126 · p126_fig011446×1015px
P151 · p151_fig011434×572px
P152 · p152_fig011437×791px
P652 · p652_fig011997×2620px
P657 · p657_fig011874×2567px
P657 · p657_fig01P657
P660 · p660_fig011874×2567px
P663 · p663_fig011874×2571px
Technical Specifications & Part Details (ATMEGA164PA-MCH)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:ATMEGA164PA-MCH (QFN-44(5x5)) is a 45-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 1.35 mm mechanical envelope (lead pitch e = 0.53 mm). Rated for 1.8V to 5.5V supply operation across -40°C to 85°C with integrated UART, SPI, ADC, PWM, JTAG / SWD, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
45 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (QFN-44(5x5))
Pin Count & Lead PitchN / e
45 Pins | Pitch e = 0.53 mm (20.9 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, ADC, PWM, JTAG / SWD, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol45 auto-grouped pins
IPC-7351B Land Pattern45 pads · Pitch 0.53mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — ATMEGA164PA / ATMEGA324A / ATMEGA324PA (4)
QFN-44(5x5) · 45P
45P5.0×5.0×1.35mmP=0.53mm
ATMEGA164PA / ATMEGA324A / ATMEGA324PA (QFN-44(5x5))
QFN-44(5x5) · 45P
45P5.0×5.0×1.35mmP=0.53mm
ATMEGA164PA / ATMEGA324A / ATMEGA324PA (QFN-44(5x5))
QFN-44(5x5) · 45P
45P5.0×5.0×1.35mmP=0.53mm
ATMEGA164PA / ATMEGA324A / ATMEGA324PA (QFN-44(5x5))
Mechanical Dimensions & Land Pattern (QFN-44(5x5))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.53mm
Pad Size (W × L)Level B
0.25 × 0.25 mm
Pins / Total PadsTopology
45P / 45Pad (BGA_GRID)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit QFN-44(5x5) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — ATMEGA164PA-MCH (QFN-44(5x5))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of ATMEGA164PA-MCH (QFN-44(5x5))?
Manufactured by MICROCHIP, the ATMEGA164PA-MCH is housed in a QFN-44(5x5) package with 45 pins and a 0.53 mm lead pitch, supporting a VCC supply range of 1.8V to 5.5V. Key pins include: 45 (EP: Exposed Thermal & Ground Pad (EP)), A1 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)), A2 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)), A3 (VCC: Power Supply Input (VCC — 1.8V ~ 5.5V VCC)), A4 (XTAL2: Multiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)), A5 (PD0: Multiplexed I/O & Peripheral Pin PD0 (General)).
What are the IPC-7351B PCB Footprint dimensions for ATMEGA164PA-MCH?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATMEGA164PA-MCH (QFN-44(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.53 mm, and 45 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATMEGA164PA-MCH?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATMEGA164PA-MCH (MICROCHIP, QFN-44(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (45 pins) & ATMEGA164PA / ATMEGA324A / ATMEGA324PA Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 45 | EP | GND | Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |
| A1 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General. |
| A2 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General. |
| A3 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V). |
| A4 | XTAL2 | Digital_IO | Signal terminal XTAL2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK. |
| A5 | PD0 | Digital_IO | Signal terminal PD0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General. |
| A6 | PD2 | Digital_IO | Signal terminal PD2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General. |
| A7 | PD3 | Digital_IO | Signal terminal PD3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General. |
| A8 | PD5 | Digital_IO | Signal terminal PD5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General. |
| A9 | PD7 | Digital_IO | Signal terminal PD7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General. |
| A10 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| A11 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General. |
| A12 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General. |
| A13 | PC4 | Digital_IO | Signal terminal PC4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General. |
| A14 | PC6 | Digital_IO | Signal terminal PC6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General. |
| A15 | AVCC | Power_In | Primary positive power supply input (AVCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V). |
| A16 | AREF | Digital_IO | Signal terminal AREF (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: AREF. Supported peripheral buses: ADC. |
| A17 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General. |
| A18 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General. |
| A19 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General. |
| A20 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General. |
| A21 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V). |
| A22 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General. |
| A23 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General. |
| A24 | PB4 | Digital_IO | Signal terminal PB4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General. |
| B1 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General. |
| B2 | RESET# | Digital_IO | Active-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals. |
| B3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| B4 | XTAL1 | Digital_IO | Signal terminal XTAL1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL1. Supported peripheral buses: RTC/CLK. |
| B5 | PD1 | Digital_IO | Signal terminal PD1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General. |
| B6 | PD4 | Digital_IO | Signal terminal PD4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General. |
| B7 | PD6 | Digital_IO | Signal terminal PD6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General. |
| B8 | VCC | Power_In | Primary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V). |
| B9 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General. |
| B10 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General. |
| B11 | PC5 | Digital_IO | Signal terminal PC5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General. |
| B12 | PC7 | Digital_IO | Signal terminal PC7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General. |
| B13 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| B14 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General. |
| B15 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General. |
| B16 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General. |
| B17 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General. |
| B18 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| B19 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General. |
| B20 | PB3 | Digital_IO | Signal terminal PB3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General. |