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ATMEGA324A-MCH (QFN-44(5x5)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATMEGA324A-MCH

MICROCHIPID: C1339016QFN-44(5x5) · 45 Pins · Pitch 0.53mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATMEGA324A-MCH (QFN-44(5x5))45EPA1PB5A2PB7A3VCCA4XTAL2A5PD0A6PD2A7PD3A8PD5A9PD7A10GNDA11PC1A12PC3A13PC4A14PC6A15AVCCA16AREFA17PA6A18PA4A19PA3A20PA1A21VCCA22PB0B20PB3B19PB1B18GNDB17PA0B16PA2B15PA5B14PA7B13GNDB12PC7B11PC5B10PC2B9PC0B8VCCB7PD6B6PD4B5PD1B4XTAL1B3GNDB2RESET#B1PB6A24PB4A23PB2Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.835.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6mm
2. 2D FOOTPRINT
B11B12B13B14B15B5B4B3B2B1B6B7B8B9B10B16B17B18B19B2045A24A23A22A21A20A19A18A17A16A15A14A13A12A11A10A9A8A7A6A5A4A3A2A1E=5.00mm · Pitch e=0.53mmD=5.00mm-4-3-2-10123443210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 5.00mm × 5.00mm · Pitch: 0.53mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (45/45)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
45EPGNDExposed Thermal & Ground Pad (EP)
A1PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
A2PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
A3VCCPowerPower Supply Input (VCC — 1.8V ~ 5.5V VCC)
A4XTAL2I/OMultiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)
A5PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
A6PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
A7PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
A8PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
A9PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
A10GNDGNDGround Reference Pin (GND)
A11PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
A12PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
A13PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
A14PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
A15AVCCPowerPower Supply Input (AVCC — 1.8V ~ 5.5V VCC)
A16AREFI/OMultiplexed I/O & Peripheral Pin AREF (ADC)
A17PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
A18PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
A19PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
A20PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
A21VCCPowerPower Supply Input (VCC — 1.8V ~ 5.5V VCC)
A22PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
A23PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
A24PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
B1PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
B2RESET#ISystem Enable & Hardware Reset (RESET#)
B3GNDGNDGround Reference Pin (GND)
B4XTAL1I/OMultiplexed I/O & Peripheral Pin XTAL1 (RTC/CLK)
B5PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
B6PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
B7PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
B8VCCPowerPower Supply Input (VCC — 1.8V ~ 5.5V VCC)
B9PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
B10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
B11PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
B12PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
B13GNDGNDGround Reference Pin (GND)
B14PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
B15PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
B16PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
B17PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
B18GNDGNDGround Reference Pin (GND)
B19PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
B20PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
PIN 45 EP
GND
Exposed Thermal & Ground Pad (EP)
Design note: Bottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 12 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATMEGA324A-MCH (MICROCHIP · QFN-44(5x5))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATMEGA324A-MCH (QFN-44(5x5)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATMEGA324A-MCH (QFN-44(5x5)) - 2. Standard Pinout (Top View)
True package pinout (45 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATMEGA324A-MCH (QFN-44(5x5)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATMEGA324A-MCH (QFN-44(5x5)) - 4. Package Dimensions (D×E×A)
QFN-44(5x5) · 5.00×5.00mm · Pitch 0.53mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATMEGA324A-MCH (QFN-44(5x5)) - 5. Recommended Land Pattern
IPC-7351B Footprint (45 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATMEGA324A-MCH (QFN-44(5x5)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (12 figures · Page 1/1)
Showing 1–12 of 12 uncropped original figures for ATMEGA164PA / ATMEGA324A / ATMEGA324PA
P1 · p01_fig01376×200px
ATMEGA324A-MCH (QFN-44(5x5)) — Introduction
Introduction
P12 · p12_fig011418×890px
ATMEGA324A-MCH (QFN-44(5x5)) — Figure 1-2. DRQFN - pinout
Figure 1-2. DRQFN - pinout
P12 · p12_fig01P12
ATMEGA324A-MCH (QFN-44(5x5)) — Datasheet Page 12 (p12_fig01)
Datasheet Page 12 (p12_fig01)
P13 · p13_fig011628×995px
ATMEGA324A-MCH (QFN-44(5x5)) — Figure 1-3. VFBGA - pinout
Figure 1-3. VFBGA - pinout
P126 · p126_fig011446×1015px
ATMEGA324A-MCH (QFN-44(5x5)) — Figure 16-5. Compare Match Output unit, schematic
Figure 16-5. Compare Match Output unit, schematic
P151 · p151_fig011434×572px
ATMEGA324A-MCH (QFN-44(5x5)) — Figure 17-5. CTC mode, timing diagram
Figure 17-5. CTC mode, timing diagram
P152 · p152_fig011437×791px
ATMEGA324A-MCH (QFN-44(5x5)) — Figure 17-6. Fast PWM mode, timing diagram
Figure 17-6. Fast PWM mode, timing diagram
P652 · p652_fig011997×2620px
ATMEGA324A-MCH (QFN-44(5x5)) — ATmega164A/PA/324A/PA/644A/PA/1284/P
ATmega164A/PA/324A/PA/644A/PA/1284/P
P657 · p657_fig011874×2567px
ATMEGA324A-MCH (QFN-44(5x5)) —  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 657 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Contact Pad Spacing | Optional Center Pad Length | Contact Pitch | Y2 X2 | 5.
 2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 657 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Contact Pad Spacing | Optional Center Pad Length | Contact Pitch | Y2 X2 | 5.
P657 · p657_fig01P657
ATMEGA324A-MCH (QFN-44(5x5)) — Datasheet Page 657 (p657_fig01)
Datasheet Page 657 (p657_fig01)
P660 · p660_fig011874×2567px
ATMEGA324A-MCH (QFN-44(5x5)) —  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 660 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Outer Contact Pad Spacing | Optional Center Pad Length | Contact Pitch | Y3 X
 2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 660 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 | Optional Center Pad Width | Outer Contact Pad Spacing | Optional Center Pad Length | Contact Pitch | Y3 X
P663 · p663_fig011874×2571px
ATMEGA324A-MCH (QFN-44(5x5)) —  2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 663 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 Contact Pad Spacing | Contact Pitch | MILLIMETERS | 0.65 BSC MIN E | MAX | 3.90 BSC Contact Pad Diameter (X
 2020 Microchip Technology Inc. Data Sheet Complete DS40002070B-page 663 | RECOMMENDED LAND PATTERN | Dimension Limits | Units | C2 Contact Pad Spacing | Contact Pitch | MILLIMETERS | 0.65 BSC MIN E | MAX | 3.90 BSC Contact Pad Diameter (X

Technical Specifications & Part Details (ATMEGA324A-MCH)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:ATMEGA324A-MCH (QFN-44(5x5)) is a 45-pin embedded microcontroller unit (mcu) featuring a 5.00 × 5.00 × 1.35 mm mechanical envelope (lead pitch e = 0.53 mm). Rated for 1.8V to 5.5V supply operation across -40°C to 85°C with integrated UART, SPI, ADC, PWM, JTAG / SWD, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V to 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
20MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
45 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
5.00 × 5.00 × 1.35 mm (A1=0.30 mm)
Package family: BGA (QFN-44(5x5))
Pin Count & Lead PitchN / e
45 Pins | Pitch e = 0.53 mm (20.9 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, ADC, PWM, JTAG / SWD, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol45 auto-grouped pins
OK
IPC-7351B Land Pattern45 pads · Pitch 0.53mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-44(5x5))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
5.00 × 5.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.35mm · e=0.53mm
Pad Size (W × L)Level B
0.25 × 0.25 mm
Pins / Total PadsTopology
45P / 45Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-44(5x5)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATMEGA324A-MCH (QFN-44(5x5))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATMEGA324A-MCH (QFN-44(5x5))?

Manufactured by MICROCHIP, the ATMEGA324A-MCH is housed in a QFN-44(5x5) package with 45 pins and a 0.53 mm lead pitch, supporting a VCC supply range of 1.8V to 5.5V. Key pins include: 45 (EP: Exposed Thermal & Ground Pad (EP)), A1 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)), A2 (PB7: Multiplexed I/O & Peripheral Pin PB7 (General)), A3 (VCC: Power Supply Input (VCC — 1.8V ~ 5.5V VCC)), A4 (XTAL2: Multiplexed I/O & Peripheral Pin XTAL2 (RTC/CLK)), A5 (PD0: Multiplexed I/O & Peripheral Pin PD0 (General)).

What are the IPC-7351B PCB Footprint dimensions for ATMEGA324A-MCH?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATMEGA324A-MCH (QFN-44(5x5)) has a nominal body envelope of 5.00 × 5.00 mm, pitch e = 0.53 mm, and 45 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATMEGA324A-MCH?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATMEGA324A-MCH (MICROCHIP, QFN-44(5x5)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (45 pins) & ATMEGA164PA / ATMEGA324A / ATMEGA324PA Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
45EPGNDBottom exposed die attach pad (EP) providing primary thermal conduction path to the PCB and low-inductance 0V ground return.
A1PB5Digital_IOSignal terminal PB5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
A2PB7Digital_IOSignal terminal PB7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
A3VCCPower_InPrimary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
A4XTAL2Digital_IOSignal terminal XTAL2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL2. Supported peripheral buses: RTC/CLK.
A5PD0Digital_IOSignal terminal PD0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
A6PD2Digital_IOSignal terminal PD2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
A7PD3Digital_IOSignal terminal PD3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
A8PD5Digital_IOSignal terminal PD5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
A9PD7Digital_IOSignal terminal PD7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
A10GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
A11PC1Digital_IOSignal terminal PC1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
A12PC3Digital_IOSignal terminal PC3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC3. Supported peripheral buses: General.
A13PC4Digital_IOSignal terminal PC4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC4. Supported peripheral buses: General.
A14PC6Digital_IOSignal terminal PC6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
A15AVCCPower_InPrimary positive power supply input (AVCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
A16AREFDigital_IOSignal terminal AREF (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: AREF. Supported peripheral buses: ADC.
A17PA6Digital_IOSignal terminal PA6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA6. Supported peripheral buses: General.
A18PA4Digital_IOSignal terminal PA4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA4. Supported peripheral buses: General.
A19PA3Digital_IOSignal terminal PA3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA3. Supported peripheral buses: General.
A20PA1Digital_IOSignal terminal PA1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA1. Supported peripheral buses: General.
A21VCCPower_InPrimary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
A22PB0Digital_IOSignal terminal PB0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB0. Supported peripheral buses: General.
A23PB2Digital_IOSignal terminal PB2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
A24PB4Digital_IOSignal terminal PB4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
B1PB6Digital_IOSignal terminal PB6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
B2RESET#Digital_IOActive-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals.
B3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
B4XTAL1Digital_IOSignal terminal XTAL1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: XTAL1. Supported peripheral buses: RTC/CLK.
B5PD1Digital_IOSignal terminal PD1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
B6PD4Digital_IOSignal terminal PD4 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
B7PD6Digital_IOSignal terminal PD6 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
B8VCCPower_InPrimary positive power supply input (VCC) operating in the 1.8V ~ 5.5V VCC domain (Max rating: 6.0V).
B9PC0Digital_IOSignal terminal PC0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
B10PC2Digital_IOSignal terminal PC2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC2. Supported peripheral buses: General.
B11PC5Digital_IOSignal terminal PC5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC5. Supported peripheral buses: General.
B12PC7Digital_IOSignal terminal PC7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
B13GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
B14PA7Digital_IOSignal terminal PA7 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA7. Supported peripheral buses: General.
B15PA5Digital_IOSignal terminal PA5 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA5. Supported peripheral buses: General.
B16PA2Digital_IOSignal terminal PA2 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA2. Supported peripheral buses: General.
B17PA0Digital_IOSignal terminal PA0 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
B18GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
B19PB1Digital_IOSignal terminal PB1 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB1. Supported peripheral buses: General.
B20PB3Digital_IOSignal terminal PB3 (I/O, 1.8V ~ 5.5V VCC domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
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