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STM32F723ZEI6 (UFBGA-144) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F723ZEI6

STUFBGA-144 · 144 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F723ZEI6 (UFBGA-144)A1PC13A2PE3A3PE2A4PE1A5PE0A6PB4A7PB3A8PD6A9PD7A10PA15A11PA14A12PA13B1PC14-OSC32_IB2PE4B3PE5B4PE6B5PB9B6PB5B7PG15B8PG12B9PD5B10PC11B11PC10B12PA12C1PC15-OSC32_OC2VBATC3PF0C4PF1C5PB8C6PB6C7PG14C8PG11C9PD4C10PC12C11VDDUSBC12PA11D1PH0-OSC_IND2VSSD3VDDD4PF2D5BOOT0D6PB7D7PG13D8PG10D9PD3D10PD1D11PA10D12PA9E1PH1-OSC_OUTE2PF3E3PF4E4PF5E5PDR_ONE6VSSE7VSSE8PG9E9PD2E10PD0E11PC9E12PA8F1NRSTF2PF7F3PF6F4VDDF5VDDF6VDDF7VDDF8VDDF9VDDF10VDDF11PC8F12PC7M12PB13M11PB12M10PB11M9PB10M8PE15M7PE7M6PF14M5PF11M4PB1M3PA7M2PA3M1VDDAL12PB15L11PB14L10PD12L9PD8L8PE14L7PE8L6PF15L5PF12L4PB0L3PA6L2PA2L1VREF+K12PD15K11PD14K10PD13K9PD9K8PE13K7PE9K6PG0K5PF13K4PC5K3PA5K2PA1K1VREF-J12PG2J11PG3J10PG4J9PD10J8PE12J7PE10J6PG1J5PB2J4PC4J3PA4J2PA0J1VSSAH12PG5H11OTG_HS_REXTH10VDD12OTGHSH9PD11H8PE11H7VCAP_1H6VSSH5BYPASS_REGH4PC3H3PC2H2PC1H1PC0G12PC6G11PG8G10VSSG9VCAP_2G8VSSG7VDDG6VDDG5VDDG4VSSG3PF8G2PF9G1PF10Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.896.591.486.481.376.271.166.061.055.950.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7-50.8-55.9-61.0-66.0-71.1-76.2-81.3-86.4-91.4-96.5mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1L1M1A2B2C2D2E2F2G2H2J2K2L2M2A3B3C3D3E3F3G3H3J3K3L3M3A4B4C4D4E4F4G4H4J4K4L4M4A5B5C5D5E5F5G5H5J5K5L5M5A6B6C6D6E6F6G6H6J6K6L6M6A7B7C7D7E7F7G7H7J7K7L7M7A8B8C8D8E8F8G8H8J8K8L8M8A9B9C9D9E9F9G9H9J9K9L9M9A10B10C10D10E10F10G10H10J10K10L10M10A11B11C11D11E11F11G11H11J11K11L11M11A12B12C12D12E12F12G12H12J12K12L12M12E=7.00mm · Pitch e=0.50mmD=7.00mm-5-4-3-2-1012345543210-1-2-3-4-5mm
3. 3D CAD MODEL
Package Body: 7.00mm × 7.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (144/144)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
A2PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
A3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
A4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
A5PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
A6PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
A7PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
A8PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
A9PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
A10PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
A11PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
A12PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
B1PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
B2PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
B3PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
B4PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
B5PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
B6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
B7PG15I/OMultiplexed I/O & Peripheral Pin PG15 (General)
B8PG12I/OMultiplexed I/O & Peripheral Pin PG12 (General)
B9PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
B10PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
B11PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
B12PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
C1PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
C2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C3PF0I/OMultiplexed I/O & Peripheral Pin PF0 (General)
C4PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
C5PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
C6PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
C7PG14I/OMultiplexed I/O & Peripheral Pin PG14 (General)
C8PG11I/OMultiplexed I/O & Peripheral Pin PG11 (General)
C9PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
C10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
C11VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
C12PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
D1PH0-OSC_INI/OMultiplexed I/O & Peripheral Pin PH0-OSC_IN (RTC/CLK)
D2VSSGNDGround Reference Pin (VSS)
D3VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D4PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
D5BOOT0IInput-Only Pin BOOT0 (General)
D6PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
D7PG13I/OMultiplexed I/O & Peripheral Pin PG13 (General)
D8PG10I/OMultiplexed I/O & Peripheral Pin PG10 (General)
D9PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
D10PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
D11PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
D12PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
E1PH1-OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1-OSC_OUT (RTC/CLK)
E2PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
E3PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
E4PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
E5PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
E6VSSGNDGround Reference Pin (VSS)
E7VSSGNDGround Reference Pin (VSS)
E8PG9I/OMultiplexed I/O & Peripheral Pin PG9 (General)
E9PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
E10PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
E11PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
E12PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
F1NRSTISystem Enable & Hardware Reset (NRST)
F2PF7I/OMultiplexed I/O & Peripheral Pin PF7 (General)
F3PF6I/OMultiplexed I/O & Peripheral Pin PF6 (General)
F4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F8VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F9VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F10VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F11PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
F12PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
G1PF10I/OMultiplexed I/O & Peripheral Pin PF10 (General)
G2PF9I/OMultiplexed I/O & Peripheral Pin PF9 (General)
G3PF8I/OMultiplexed I/O & Peripheral Pin PF8 (General)
G4VSSGNDGround Reference Pin (VSS)
G5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G7VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
G8VSSGNDGround Reference Pin (VSS)
G9VCAP_2I/OMultiplexed I/O & Peripheral Pin VCAP_2 (General)
G10VSSGNDGround Reference Pin (VSS)
G11PG8I/OMultiplexed I/O & Peripheral Pin PG8 (General)
G12PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
H1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
H2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
H3PC2I/OMultiplexed I/O & Peripheral Pin PC2 (General)
H4PC3I/OMultiplexed I/O & Peripheral Pin PC3 (General)
H5BYPASS_REGI/OMultiplexed I/O & Peripheral Pin BYPASS_REG (General)
H6VSSGNDGround Reference Pin (VSS)
H7VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
H8PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
H9PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
H10VDD12OTGHSPowerPower Supply Input (VDD12OTGHS — 3.3V VDD (Max 4.0V))
H11OTG_HS_REXTI/OMultiplexed I/O & Peripheral Pin OTG_HS_REXT (General)
H12PG5I/OMultiplexed I/O & Peripheral Pin PG5 (General)
J1VSSAGNDGround Reference Pin (VSSA)
J2PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
J3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
J4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
J5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
J6PG1I/OMultiplexed I/O & Peripheral Pin PG1 (General)
J7PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
J8PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
J9PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
J10PG4I/OMultiplexed I/O & Peripheral Pin PG4 (General)
J11PG3I/OMultiplexed I/O & Peripheral Pin PG3 (General)
J12PG2I/OMultiplexed I/O & Peripheral Pin PG2 (General)
K1VREF-AnalogMultiplexed I/O & Peripheral Pin VREF- (General)
K2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
K3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
K4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
K5PF13I/OMultiplexed I/O & Peripheral Pin PF13 (General)
K6PG0I/OMultiplexed I/O & Peripheral Pin PG0 (General)
K7PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
K8PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
K9PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
K10PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
K11PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
K12PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
L1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
L2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
L3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
L4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
L5PF12I/OMultiplexed I/O & Peripheral Pin PF12 (General)
L6PF15I/OMultiplexed I/O & Peripheral Pin PF15 (General)
L7PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
L8PE14I/OMultiplexed I/O & Peripheral Pin PE14 (General)
L9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
L10PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
L11PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
L12PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
M1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
M2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
M3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
M4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
M5PF11I/OMultiplexed I/O & Peripheral Pin PF11 (General)
M6PF14I/OMultiplexed I/O & Peripheral Pin PF14 (General)
M7PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
M8PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
M9PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
M10PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
M11PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
M12PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
PIN A1 PC13
I/O
Multiplexed I/O & Peripheral Pin PC13 (General)
Design note: Signal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 30 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F723ZEI6 (ST · UFBGA-144)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F723ZEI6 (UFBGA-144) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F723ZEI6 (UFBGA-144) - 2. Standard Pinout (Top View)
True package pinout (144 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F723ZEI6 (UFBGA-144) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F723ZEI6 (UFBGA-144) - 4. Package Dimensions (D×E×A)
UFBGA-144 · 7.00×7.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F723ZEI6 (UFBGA-144) - 5. Recommended Land Pattern
IPC-7351B Footprint (144 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F723ZEI6 (UFBGA-144) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (30 figures · Page 1/3)
Showing 1–12 of 30 uncropped original figures for STM32F723 / STM32F722
P56 · p56_fig01EXACT PACKAGE
STM32F723ZEI6 (UFBGA-144) — Figure 21. STM32F723xx UFBGA144 ballout (with OTG PHY HS)
Figure 21. STM32F723xx UFBGA144 ballout (with OTG PHY HS)
P215 · p215_fig01EXACT PACKAGE
STM32F723ZEI6 (UFBGA-144) — Figure 92. UFBGA144 outline
Figure 92. UFBGA144 outline
P216 · p216_fig01EXACT PACKAGE
STM32F723ZEI6 (UFBGA-144) — Figure 93. UFBGA144 recommended footprint
Figure 93. UFBGA144 recommended footprint
P216 · p216_fig02EXACT PACKAGE
STM32F723ZEI6 (UFBGA-144) — Figure 93. UFBGA144 recommended footprint
Figure 93. UFBGA144 recommended footprint
P1 · p01_fig01881×620px
STM32F723ZEI6 (UFBGA-144) — • 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
• 3×12-bit, 2.4 MSPS ADC: up to 24 channels and 7.2 MSPS in triple interleaved mode
P50 · p50_fig011546×1305px
STM32F723ZEI6 (UFBGA-144) — Figure 15. STM32F722xx LQFP64 pinout
Figure 15. STM32F722xx LQFP64 pinout
P51 · p51_fig011546×1375px
STM32F723ZEI6 (UFBGA-144) — Figure 16. STM32F722xx LQFP100 pinout
Figure 16. STM32F722xx LQFP100 pinout
P102 · p102_fig011546×1696px
STM32F723ZEI6 (UFBGA-144) — Figure 28. STM32F722xx power supply scheme
Figure 28. STM32F722xx power supply scheme
P103 · p103_fig011546×2240px
STM32F723ZEI6 (UFBGA-144) — Figure 29. STM32F723xx power supply scheme
Figure 29. STM32F723xx power supply scheme
P134 · p134_fig011546×487px
STM32F723ZEI6 (UFBGA-144) — Figure 39. Typical application with an 8 MHz crystal
Figure 39. Typical application with an 8 MHz crystal
P203 · p203_fig011546×1030px
STM32F723ZEI6 (UFBGA-144) — Figure 81. LQFP64 recommended footprint
Figure 81. LQFP64 recommended footprint
P219 · p219_fig011557×1183px
STM32F723ZEI6 (UFBGA-144) — Figure 96. UFBGA176+25 recommended footprint
Figure 96. UFBGA176+25 recommended footprint
Page 1 / 3 (30 extracted figures)

Technical Specifications & Part Details (STM32F723ZEI6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F723ZEI6 (UFBGA-144) is a 144-pin embedded microcontroller unit (mcu) featuring a 7.00 × 7.00 × 0.65 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
216 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
7.00 × 7.00 × 0.65 mm (A1=0.20 mm)
Package family: BGA (UFBGA-144)
Pin Count & Lead PitchN / e
144 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol144 auto-grouped pins
OK
IPC-7351B Land Pattern144 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32F723 / STM32F722 (11)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (UFBGA-144)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
7.00 × 7.00 mm
Height (A) & Pitch (e)IPC-7351B
A=0.65mm · e=0.50mm
Pad Size (W × L)Level B
0.22 × 0.22 mm
Pins / Total PadsTopology
144P / 144Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
UFBGA-144
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F723ZEI6 (UFBGA-144)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F723ZEI6 (UFBGA-144)?

Manufactured by ST, the STM32F723ZEI6 is housed in a UFBGA-144 package with 144 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: A1 (PC13: Multiplexed I/O & Peripheral Pin PC13 (General)), A2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), A4 (PE1: Multiplexed I/O & Peripheral Pin PE1 (General)), A5 (PE0: Multiplexed I/O & Peripheral Pin PE0 (General)), A6 (PB4: Multiplexed I/O & Peripheral Pin PB4 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32F723ZEI6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F723ZEI6 (UFBGA-144) has a nominal body envelope of 7.00 × 7.00 mm, pitch e = 0.50 mm, and 144 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F723ZEI6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F723ZEI6 (ST, UFBGA-144) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (144 pins) & STM32F723 / STM32F722 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
A2PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
A3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
A4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
A5PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
A6PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
A7PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
A8PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
A9PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
A10PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
A11PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
A12PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
B1PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
B2PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
B3PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
B4PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
B5PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
B6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
B7PG15Digital_IOSignal terminal PG15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG15. Supported peripheral buses: General.
B8PG12Digital_IOSignal terminal PG12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG12. Supported peripheral buses: General.
B9PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
B10PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
B11PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
B12PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
C1PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
C2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C3PF0Digital_IOSignal terminal PF0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General.
C4PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
C5PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
C6PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
C7PG14Digital_IOSignal terminal PG14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG14. Supported peripheral buses: General.
C8PG11Digital_IOSignal terminal PG11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG11. Supported peripheral buses: General.
C9PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
C10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
C11VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C12PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
D1PH0-OSC_INDigital_IOSignal terminal PH0-OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0-OSC_IN. Supported peripheral buses: RTC/CLK.
D2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D3VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D4PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
D5BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
D6PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
D7PG13Digital_IOSignal terminal PG13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG13. Supported peripheral buses: General.
D8PG10Digital_IOSignal terminal PG10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG10. Supported peripheral buses: General.
D9PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
D10PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
D11PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
D12PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
E1PH1-OSC_OUTDigital_IOSignal terminal PH1-OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1-OSC_OUT. Supported peripheral buses: RTC/CLK.
E2PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
E3PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
E4PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
E5PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
E6VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E8PG9Digital_IOSignal terminal PG9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG9. Supported peripheral buses: General.
E9PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
E10PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
E11PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
E12PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
F1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F2PF7Digital_IOSignal terminal PF7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF7. Supported peripheral buses: General.
F3PF6Digital_IOSignal terminal PF6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF6. Supported peripheral buses: General.
F4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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