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CH352L (LQFP-100(14x14)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH352L

WCHID: C125755LQFP-100(14x14) · 100 Pins · Pitch 0.50mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH352L (LQFP-100(14x14))1NC2NC3GND4GND5AD196AD187AD178AD169CBE3～CBE010FRAME11SDA12TRDY13DEVSEL14INTA15PAR16CBE3～CBE017AD1518AD1419AD1320AD1221AD1122AD1023VCC24GND25NC26NC27NC28GND29NC30AD931AD832CBE3～CBE033AD734AD635AD536AD437AD338AD239AD140AD041TXD42RTS43DTR44RXD45DCD46RI47DSR48CTS49NC50NC100NC99NC98VCC97VCC96AD2095AD2194AD2293AD2392IDSEL91CBE3～CBE090AD2489AD2588AD2687AD2786AD2885AD2984AD3083AD3182CLK81RST80RTS179TNOW78VCC77VCC76NC75NC74NC73GND72NC71SCL70CTS169DSR168RI167DCD166RXD165RSVD64RSVD63HALF#62CK1S061CK1S160CKS059CKS158INV#57TXD156DTR155XO54XI53GND52NC51NCGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.268.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100E=14.00mm · Pitch e=0.50mmD=14.00mm-12-10-8-6-4-2024681012121086420-2-4-6-8-10-12mm
3. 3D CAD MODEL
Package Body: 14.00mm × 14.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1NCI/OMultiplexed I/O & Peripheral Pin NC (General)
2NCI/OMultiplexed I/O & Peripheral Pin NC (General)
3GNDGNDGround Reference Pin (GND)
4GNDGNDGround Reference Pin (GND)
5AD19I/OMultiplexed I/O & Peripheral Pin AD19 (General)
6AD18I/OMultiplexed I/O & Peripheral Pin AD18 (General)
7AD17I/OMultiplexed I/O & Peripheral Pin AD17 (General)
8AD16I/OMultiplexed I/O & Peripheral Pin AD16 (General)
9CBE3～CBE0I/OMultiplexed I/O & Peripheral Pin CBE3～CBE0 (General)
10FRAMEI/OMultiplexed I/O & Peripheral Pin FRAME (General)
11SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
12TRDYI/OMultiplexed I/O & Peripheral Pin TRDY (General)
13DEVSELI/OMultiplexed I/O & Peripheral Pin DEVSEL (General)
14INTAI/OMultiplexed I/O & Peripheral Pin INTA (General)
15PARI/OMultiplexed I/O & Peripheral Pin PAR (General)
16CBE3～CBE0I/OMultiplexed I/O & Peripheral Pin CBE3～CBE0 (General)
17AD15I/OMultiplexed I/O & Peripheral Pin AD15 (General)
18AD14I/OMultiplexed I/O & Peripheral Pin AD14 (General)
19AD13I/OMultiplexed I/O & Peripheral Pin AD13 (General)
20AD12I/OMultiplexed I/O & Peripheral Pin AD12 (General)
21AD11I/OMultiplexed I/O & Peripheral Pin AD11 (General)
22AD10I/OMultiplexed I/O & Peripheral Pin AD10 (General)
23VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
24GNDGNDGround Reference Pin (GND)
25NCI/OMultiplexed I/O & Peripheral Pin NC (General)
26NCI/OMultiplexed I/O & Peripheral Pin NC (General)
27NCI/OMultiplexed I/O & Peripheral Pin NC (General)
28GNDGNDGround Reference Pin (GND)
29NCI/OMultiplexed I/O & Peripheral Pin NC (General)
30AD9I/OMultiplexed I/O & Peripheral Pin AD9 (General)
31AD8I/OMultiplexed I/O & Peripheral Pin AD8 (General)
32CBE3～CBE0I/OMultiplexed I/O & Peripheral Pin CBE3～CBE0 (General)
33AD7I/OMultiplexed I/O & Peripheral Pin AD7 (General)
34AD6I/OMultiplexed I/O & Peripheral Pin AD6 (General)
35AD5I/OMultiplexed I/O & Peripheral Pin AD5 (General)
36AD4I/OMultiplexed I/O & Peripheral Pin AD4 (General)
37AD3I/OMultiplexed I/O & Peripheral Pin AD3 (General)
38AD2I/OMultiplexed I/O & Peripheral Pin AD2 (General)
39AD1I/OMultiplexed I/O & Peripheral Pin AD1 (General)
40AD0I/OMultiplexed I/O & Peripheral Pin AD0 (General)
41TXDI/OTXD (UART)
42RTSI/OMultiplexed I/O & Peripheral Pin RTS (UART)
43DTRI/OMultiplexed I/O & Peripheral Pin DTR (UART)
44RXDI/ORXD (UART)
45DCDI/OMultiplexed I/O & Peripheral Pin DCD (General)
46RII/OMultiplexed I/O & Peripheral Pin RI (General)
47DSRI/OMultiplexed I/O & Peripheral Pin DSR (UART)
48CTSI/OMultiplexed I/O & Peripheral Pin CTS (UART)
49NCI/OMultiplexed I/O & Peripheral Pin NC (General)
50NCI/OMultiplexed I/O & Peripheral Pin NC (General)
51NCI/OMultiplexed I/O & Peripheral Pin NC (General)
52NCI/OMultiplexed I/O & Peripheral Pin NC (General)
53GNDGNDGround Reference Pin (GND)
54XII/OXI (RTC/CLK)
55XOI/OXO (RTC/CLK)
56DTR1I/OMultiplexed I/O & Peripheral Pin DTR1 (UART)
57TXD1I/OTXD1 (UART)
58INV#I/OMultiplexed I/O & Peripheral Pin INV# (General)
59CKS1I/OMultiplexed I/O & Peripheral Pin CKS1 (General)
60CKS0I/OMultiplexed I/O & Peripheral Pin CKS0 (General)
61CK1S1I/OMultiplexed I/O & Peripheral Pin CK1S1 (General)
62CK1S0I/OMultiplexed I/O & Peripheral Pin CK1S0 (General)
63HALF#I/OMultiplexed I/O & Peripheral Pin HALF# (General)
64RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
65RSVDI/OMultiplexed I/O & Peripheral Pin RSVD (General)
66RXD1I/ORXD1 (UART)
67DCD1I/OMultiplexed I/O & Peripheral Pin DCD1 (General)
68RI1I/OMultiplexed I/O & Peripheral Pin RI1 (General)
69DSR1I/OMultiplexed I/O & Peripheral Pin DSR1 (UART)
70CTS1I/OMultiplexed I/O & Peripheral Pin CTS1 (UART)
71SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
72NCI/OMultiplexed I/O & Peripheral Pin NC (General)
73GNDGNDGround Reference Pin (GND)
74NCI/OMultiplexed I/O & Peripheral Pin NC (General)
75NCI/OMultiplexed I/O & Peripheral Pin NC (General)
76NCI/OMultiplexed I/O & Peripheral Pin NC (General)
77VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
78VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
79TNOWI/OMultiplexed I/O & Peripheral Pin TNOW (General)
80RTS1I/OMultiplexed I/O & Peripheral Pin RTS1 (UART)
81RSTI/OMultiplexed I/O & Peripheral Pin RST (General)
82CLKI/OMultiplexed I/O & Peripheral Pin CLK (General)
83AD31I/OMultiplexed I/O & Peripheral Pin AD31 (General)
84AD30I/OMultiplexed I/O & Peripheral Pin AD30 (General)
85AD29I/OMultiplexed I/O & Peripheral Pin AD29 (General)
86AD28I/OMultiplexed I/O & Peripheral Pin AD28 (General)
87AD27I/OMultiplexed I/O & Peripheral Pin AD27 (General)
88AD26I/OMultiplexed I/O & Peripheral Pin AD26 (General)
89AD25I/OMultiplexed I/O & Peripheral Pin AD25 (General)
90AD24I/OMultiplexed I/O & Peripheral Pin AD24 (General)
91CBE3～CBE0I/OMultiplexed I/O & Peripheral Pin CBE3～CBE0 (General)
92IDSELI/OMultiplexed I/O & Peripheral Pin IDSEL (General)
93AD23I/OMultiplexed I/O & Peripheral Pin AD23 (General)
94AD22I/OMultiplexed I/O & Peripheral Pin AD22 (General)
95AD21I/OMultiplexed I/O & Peripheral Pin AD21 (General)
96AD20I/OMultiplexed I/O & Peripheral Pin AD20 (General)
97VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
98VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
99NCI/OMultiplexed I/O & Peripheral Pin NC (General)
100NCI/OMultiplexed I/O & Peripheral Pin NC (General)
PIN 1 NC
I/O
Multiplexed I/O & Peripheral Pin NC (General)
Design note: Signal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 7 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH352L (WCH · LQFP-100(14x14))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH352L (LQFP-100(14x14)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH352L (LQFP-100(14x14)) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH352L (LQFP-100(14x14)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH352L (LQFP-100(14x14)) - 4. Package Dimensions (D×E×A)
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH352L (LQFP-100(14x14)) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH352L (LQFP-100(14x14)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (7 figures · Page 1/1)
Showing 1–7 of 7 uncropped original figures for CH352
P3 · p03_fig01EXACT PACKAGE
CH352L (LQFP-100(14x14)) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号 LQFP-100 14mm x 14mm 0.5mm 19.7mil 标准LQFP100 贴片 CH352L
封装形式 塑体宽度 引脚间距 封装说明 订货型号 LQFP-100 14mm x 14mm 0.5mm 19.7mil 标准LQFP100 贴片 CH352L
P1 · p01_fig011551×1715px
CH352L (LQFP-100(14x14)) — 2、特点
2、特点
P2 · p02_fig011274×1099px
CH352L (LQFP-100(14x14)) — 3、封装
3、封装
P2 · p02_fig01P2
CH352L (LQFP-100(14x14)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig01P3
CH352L (LQFP-100(14x14)) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)
P4 · p04_fig011732×1793px
CH352L (LQFP-100(14x14)) — CH352 芯片具有两种功能模式：双串口功能模式、串口+并口功能模式。 SCL 引脚用于配置芯片的功能，SDA 引脚用于使能外部的串行EEPROM 配置芯片，参考下表。
CH352 芯片具有两种功能模式：双串口功能模式、串口+并口功能模式。 SCL 引脚用于配置芯片的功能，SDA 引脚用于使能外部的串行EEPROM 配置芯片，参考下表。
P11 · p11_fig011944×1521px
CH352L (LQFP-100(14x14)) — 9.1. 双RS232 串口（下图）
9.1. 双RS232 串口（下图）

Technical Specifications & Part Details (CH352L)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH352L (LQFP-100(14x14)) is a 100-pin standard electronic & interconnect component featuring a 14.00 × 14.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, IrDA, I2C, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
1184MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, IrDA, I2C, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-100(14x14))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-100(14x14)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH352L (LQFP-100(14x14))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH352L (LQFP-100(14x14))?

Manufactured by WCH, the CH352L is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 2 (NC: Multiplexed I/O & Peripheral Pin NC (General)), 3 (GND: Ground Reference Pin (GND)), 4 (GND: Ground Reference Pin (GND)), 5 (AD19: Multiplexed I/O & Peripheral Pin AD19 (General)), 6 (AD18: Multiplexed I/O & Peripheral Pin AD18 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH352L?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH352L (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH352L?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH352L (WCH, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & CH352 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
2NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5AD19Digital_IOSignal terminal AD19 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD19. Supported peripheral buses: General.
6AD18Digital_IOSignal terminal AD18 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD18. Supported peripheral buses: General.
7AD17Digital_IOSignal terminal AD17 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD17. Supported peripheral buses: General.
8AD16Digital_IOSignal terminal AD16 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD16. Supported peripheral buses: General.
9CBE3～CBE0Digital_IOSignal terminal CBE3～CBE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CBE3～CBE0. Supported peripheral buses: General.
10FRAMEDigital_IOSignal terminal FRAME (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: FRAME. Supported peripheral buses: General.
11SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
12TRDYDigital_IOSignal terminal TRDY (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TRDY. Supported peripheral buses: General.
13DEVSELDigital_IOSignal terminal DEVSEL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DEVSEL. Supported peripheral buses: General.
14INTADigital_IOSignal terminal INTA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INTA. Supported peripheral buses: General.
15PARDigital_IOSignal terminal PAR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PAR. Supported peripheral buses: General.
16CBE3～CBE0Digital_IOSignal terminal CBE3～CBE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CBE3～CBE0. Supported peripheral buses: General.
17AD15Digital_IOSignal terminal AD15 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD15. Supported peripheral buses: General.
18AD14Digital_IOSignal terminal AD14 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD14. Supported peripheral buses: General.
19AD13Digital_IOSignal terminal AD13 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD13. Supported peripheral buses: General.
20AD12Digital_IOSignal terminal AD12 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD12. Supported peripheral buses: General.
21AD11Digital_IOSignal terminal AD11 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD11. Supported peripheral buses: General.
22AD10Digital_IOSignal terminal AD10 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD10. Supported peripheral buses: General.
23VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
24GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
25NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
26NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
27NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
28GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
29NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
30AD9Digital_IOSignal terminal AD9 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD9. Supported peripheral buses: General.
31AD8Digital_IOSignal terminal AD8 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD8. Supported peripheral buses: General.
32CBE3～CBE0Digital_IOSignal terminal CBE3～CBE0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CBE3～CBE0. Supported peripheral buses: General.
33AD7Digital_IOSignal terminal AD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD7. Supported peripheral buses: General.
34AD6Digital_IOSignal terminal AD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD6. Supported peripheral buses: General.
35AD5Digital_IOSignal terminal AD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD5. Supported peripheral buses: General.
36AD4Digital_IOSignal terminal AD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD4. Supported peripheral buses: General.
37AD3Digital_IOSignal terminal AD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD3. Supported peripheral buses: General.
38AD2Digital_IOSignal terminal AD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD2. Supported peripheral buses: General.
39AD1Digital_IOSignal terminal AD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD1. Supported peripheral buses: General.
40AD0Digital_IOSignal terminal AD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AD0. Supported peripheral buses: General.
41TXDDigital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
42RTSDigital_IOSignal terminal RTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RTS. Supported peripheral buses: UART.
43DTRDigital_IOSignal terminal DTR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR. Supported peripheral buses: UART.
44RXDDigital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
45DCDDigital_IOSignal terminal DCD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD. Supported peripheral buses: General.
46RIDigital_IOSignal terminal RI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI. Supported peripheral buses: General.
47DSRDigital_IOSignal terminal DSR (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR. Supported peripheral buses: UART.
48CTSDigital_IOSignal terminal CTS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS. Supported peripheral buses: UART.
49NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
50NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
51NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
52NCNCSignal terminal NC (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: NC. Supported peripheral buses: General.
53GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
54XIDigital_IO12 MHz crystal oscillator input (XI); requires a 22pF load capacitor to GND (internally clocked on CH340C).
55XODigital_IO12 MHz crystal oscillator inverted output (XO); connect to crystal terminal and 22pF load capacitor to GND.
56DTR1Digital_IOSignal terminal DTR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DTR1. Supported peripheral buses: UART.
57TXD1Digital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
58INV#Digital_IOSignal terminal INV# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INV#. Supported peripheral buses: General.
59CKS1Digital_IOSignal terminal CKS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CKS1. Supported peripheral buses: General.
60CKS0Digital_IOSignal terminal CKS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CKS0. Supported peripheral buses: General.
61CK1S1Digital_IOSignal terminal CK1S1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CK1S1. Supported peripheral buses: General.
62CK1S0Digital_IOSignal terminal CK1S0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CK1S0. Supported peripheral buses: General.
63HALF#Digital_IOSignal terminal HALF# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: HALF#. Supported peripheral buses: General.
64RSVDNCSignal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General.
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