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ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Symbol, Footprint IPC-7351B & 3D STEP Model

ATSAMC21J18A-MUT

MICROCHIPID: C124135QFN-64-EP(9x9) · 65 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · ATSAMC21J18A-MUT (QFN-64-EP(9x9))1IO12PA013PA024PA035Bit6PB057GNDANA8VDDANA9PB0610PB0711PB0812PB0913Bit14PA0515PA0616PA0717PA0818PA0919PA1020PA1121Bit22GND23PB1024PB1125PB1226PB1327PB1428PB1529PA1230PA1331PA1432PA1533GND65PAD64PB0363PB0262PB0161PB0060PB3159PB3058PA3157PA3056VDDIN55VDDCORE54GND53PA2852RESET51PA2750PA2349PB2248VDDIO47GND46PA2545PA2444PA2343PA2242PA2141PA2040PB1739PB1638PA1937PA1836PA1735PA1634VDDIOGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.848.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465E=9.00mm · Pitch e=0.50mmD=9.00mm-7-5-3-113577531-1-3-5-7mm
3. 3D CAD MODEL
Package Body: 9.00mm × 9.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (65/65)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1IO1I/OGeneral Purpose Digital I/O Pin IO1
2PA01I/OMultiplexed I/O & Peripheral Pin PA01 (General)
3PA02I/OMultiplexed I/O & Peripheral Pin PA02 (General)
4PA03I/OMultiplexed I/O & Peripheral Pin PA03 (General)
5BitI/OMultiplexed I/O & Peripheral Pin Bit (General)
6PB05I/OMultiplexed I/O & Peripheral Pin PB05 (General)
7GNDANAGNDGround Reference Pin (GNDANA)
8VDDANAPowerPower Supply Input (VDDANA — 2.7V – 5.5V)
9PB06I/OMultiplexed I/O & Peripheral Pin PB06 (General)
10PB07I/OMultiplexed I/O & Peripheral Pin PB07 (General)
11PB08I/OMultiplexed I/O & Peripheral Pin PB08 (General)
12PB09I/OMultiplexed I/O & Peripheral Pin PB09 (General)
13BitI/OMultiplexed I/O & Peripheral Pin Bit (General)
14PA05I/OMultiplexed I/O & Peripheral Pin PA05 (General)
15PA06I/OMultiplexed I/O & Peripheral Pin PA06 (General)
16PA07I/OMultiplexed I/O & Peripheral Pin PA07 (General)
17PA08I/OMultiplexed I/O & Peripheral Pin PA08 (General)
18PA09I/OMultiplexed I/O & Peripheral Pin PA09 (General)
19PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
20PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
21BitI/OMultiplexed I/O & Peripheral Pin Bit (General)
22GNDGNDGround Reference Pin (GND)
23PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
24PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
25PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
26PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
27PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
28PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
29PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
30PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
31PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
32PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
33GNDGNDGround Reference Pin (GND)
34VDDIOPowerPower Supply Input (VDDIO — 2.7V – 5.5V)
35PA16I/OMultiplexed I/O & Peripheral Pin PA16 (General)
36PA17I/OMultiplexed I/O & Peripheral Pin PA17 (General)
37PA18I/OMultiplexed I/O & Peripheral Pin PA18 (General)
38PA19I/OMultiplexed I/O & Peripheral Pin PA19 (General)
39PB16I/OMultiplexed I/O & Peripheral Pin PB16 (General)
40PB17I/OMultiplexed I/O & Peripheral Pin PB17 (General)
41PA20I/OMultiplexed I/O & Peripheral Pin PA20 (General)
42PA21I/OMultiplexed I/O & Peripheral Pin PA21 (General)
43PA22I/OMultiplexed I/O & Peripheral Pin PA22 (General)
44PA23I/OMultiplexed I/O & Peripheral Pin PA23 (General)
45PA24I/OMultiplexed I/O & Peripheral Pin PA24 (General)
46PA25I/OMultiplexed I/O & Peripheral Pin PA25 (General)
47GNDGNDGround Reference Pin (GND)
48VDDIOPowerPower Supply Input (VDDIO — 2.7V – 5.5V)
49PB22I/OMultiplexed I/O & Peripheral Pin PB22 (General)
50PA23I/OMultiplexed I/O & Peripheral Pin PA23 (General)
51PA27I/OMultiplexed I/O & Peripheral Pin PA27 (General)
52RESETISystem Enable & Hardware Reset (RESET)
53PA28I/OMultiplexed I/O & Peripheral Pin PA28 (General)
54GNDGNDGround Reference Pin (GND)
55VDDCOREPowerPower Supply Input (VDDCORE — 2.7V – 5.5V)
56VDDINPowerPower Supply Input (VDDIN — 2.7V – 5.5V)
57PA30I/OMultiplexed I/O & Peripheral Pin PA30 (General)
58PA31I/OMultiplexed I/O & Peripheral Pin PA31 (General)
59PB30I/OMultiplexed I/O & Peripheral Pin PB30 (General)
60PB31I/OMultiplexed I/O & Peripheral Pin PB31 (General)
61PB00I/OMultiplexed I/O & Peripheral Pin PB00 (General)
62PB01I/OMultiplexed I/O & Peripheral Pin PB01 (General)
63PB02I/OMultiplexed I/O & Peripheral Pin PB02 (General)
64PB03I/OMultiplexed I/O & Peripheral Pin PB03 (General)
65PADI/OMultiplexed I/O & Peripheral Pin PAD (General)
PIN 1 IO1
I/O
General Purpose Digital I/O Pin IO1
Design note: 3.3V logic domain (3.6V absolute max), 40mA max drive current.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 18 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: ATSAMC21J18A-MUT (MICROCHIP · QFN-64-EP(9x9))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) - 2. Standard Pinout (Top View)
True package pinout (65 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) - 4. Package Dimensions (D×E×A)
QFN-64-EP(9x9) · 9.00×9.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) - 5. Recommended Land Pattern
IPC-7351B Footprint (65 Pads)Expand ›
6. Application SchematicSCHEMATIC
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (18 figures · Page 1/2)
Showing 1–12 of 18 uncropped original figures for ATSAMC21J18A
P23 · p23_fig01EXACT PACKAGE
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — 4.3.1 VQFN64/TQFP64
4.3.1 VQFN64/TQFP64
P1 · p01_fig01456×280px
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — 32-bit Arm Cortex-M0+ with 5V Support, CAN-FD, PTC, and
32-bit Arm Cortex-M0+ with 5V Support, CAN-FD, PTC, and
P23 · p23_fig02684×418px
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — PA08 17 PA09 18 PA10 19 PA11 20 VDDIO 21 GND 22 PB10 23 PB11
PA08 17 PA09 18 PA10 19 PA11 20 VDDIO 21 GND 22 PB10 23 PB11
P23 · p23_fig01P23
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Datasheet Page 23 (p23_fig01)
Datasheet Page 23 (p23_fig01)
P438 · p438_fig011478×828px
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Figure 28-4. I/O configuration - Standard Input
Figure 28-4. I/O configuration - Standard Input
P438 · p438_fig02871×755px
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Figure 28-4. I/O configuration - Standard Input
Figure 28-4. I/O configuration - Standard Input
P1135 · p1135_fig011284×999px
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Units Dimension Limits
Units Dimension Limits
P1135 · p1135_fig01P1135
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Datasheet Page 1135 (p1135_fig01)
Datasheet Page 1135 (p1135_fig01)
P1136 · p1136_fig011328×1399px
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Contact Pad Length (X64) Contact Pad Width (X64)
Contact Pad Length (X64) Contact Pad Width (X64)
P1136 · p1136_fig01P1136
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Datasheet Page 1136 (p1136_fig01)
Datasheet Page 1136 (p1136_fig01)
P1140 · p1140_fig011244×1410px
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Contact Pad Length (X64) Contact Pad Width (X64)
Contact Pad Length (X64) Contact Pad Width (X64)
P1144 · p1144_fig011569×1921px
ATSAMC21J18A-MUT (QFN-64-EP(9x9)) — Table 52-10. Device and Package Maximum Weight
Table 52-10. Device and Package Maximum Weight
Page 1 / 2 (18 extracted figures)

Technical Specifications & Part Details (ATSAMC21J18A-MUT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:ATSAMC21J18A-MUT (QFN-64-EP(9x9)) is a 64-pin standard electronic & interconnect component featuring a 9.00 × 9.00 × 1.00 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 2.7V – 5.5V supply operation across -40°C to +125°C with integrated UART, SPI, I2C, CAN, ADC, DAC, PWM, JTAG / SWD interfaces.
Operating Supply VoltageV_CC / V_DD
2.7V – 5.5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C to +125°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
48 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.00 × 9.00 × 1.00 mm (A1=0.03 mm)
Package family: QFN (QFN-64-EP(9x9))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, CAN, ADC, DAC, PWM, JTAG / SWD
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol65 auto-grouped pins
OK
IPC-7351B Land Pattern65 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteEPAD 4.70×4.70mm windowed grid
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (QFN-64-EP(9x9))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.00 × 9.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.00mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 0.80 mm
Pins / Total PadsTopology
65P / 65Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
QFN-64-EP(9x9)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — ATSAMC21J18A-MUT (QFN-64-EP(9x9))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of ATSAMC21J18A-MUT (QFN-64-EP(9x9))?

Manufactured by MICROCHIP, the ATSAMC21J18A-MUT is housed in a QFN-64-EP(9x9) package with 65 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 2.7V – 5.5V. Key pins include: 1 (IO1: General Purpose Digital I/O Pin IO1), 2 (PA01: Multiplexed I/O & Peripheral Pin PA01 (General)), 3 (PA02: Multiplexed I/O & Peripheral Pin PA02 (General)), 4 (PA03: Multiplexed I/O & Peripheral Pin PA03 (General)), 5 (Bit: Multiplexed I/O & Peripheral Pin Bit (General)), 6 (PB05: Multiplexed I/O & Peripheral Pin PB05 (General)).

What are the IPC-7351B PCB Footprint dimensions for ATSAMC21J18A-MUT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), ATSAMC21J18A-MUT (QFN-64-EP(9x9)) has a nominal body envelope of 9.00 × 9.00 mm, pitch e = 0.50 mm, and 65 copper pads plus a central exposed thermal pad (EPAD) of 4.70 × 4.70 mm with a 60% IPC-7525 windowed solder paste grid.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for ATSAMC21J18A-MUT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for ATSAMC21J18A-MUT (MICROCHIP, QFN-64-EP(9x9)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (65 pins) & ATSAMC21J18A Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1IO1Digital_IOGeneral Purpose Digital I/O Pin IO1
2PA01Digital_IOSignal terminal PA01 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA01. Supported peripheral buses: General.
3PA02Digital_IOSignal terminal PA02 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA02. Supported peripheral buses: General.
4PA03Digital_IOSignal terminal PA03 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA03. Supported peripheral buses: General.
5BitDigital_IOSignal terminal Bit (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: Bit. Supported peripheral buses: General.
6PB05Digital_IOSignal terminal PB05 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB05. Supported peripheral buses: General.
7GNDANAGND0V electrical ground return terminal (GNDANA) for internal core logic, I/O drivers, and analog sub-blocks.
8VDDANAPower_InPrimary positive power supply input (VDDANA) operating in the 2.7V – 5.5V domain (Max rating: 5.5V).
9PB06Digital_IOSignal terminal PB06 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB06. Supported peripheral buses: General.
10PB07Digital_IOSignal terminal PB07 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB07. Supported peripheral buses: General.
11PB08Digital_IOSignal terminal PB08 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB08. Supported peripheral buses: General.
12PB09Digital_IOSignal terminal PB09 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB09. Supported peripheral buses: General.
13BitDigital_IOSignal terminal Bit (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: Bit. Supported peripheral buses: General.
14PA05Digital_IOSignal terminal PA05 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA05. Supported peripheral buses: General.
15PA06Digital_IOSignal terminal PA06 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA06. Supported peripheral buses: General.
16PA07Digital_IOSignal terminal PA07 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA07. Supported peripheral buses: General.
17PA08Digital_IOSignal terminal PA08 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA08. Supported peripheral buses: General.
18PA09Digital_IOSignal terminal PA09 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA09. Supported peripheral buses: General.
19PA10Digital_IOSignal terminal PA10 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
20PA11Digital_IOSignal terminal PA11 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
21BitDigital_IOSignal terminal Bit (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: Bit. Supported peripheral buses: General.
22GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
23PB10Digital_IOSignal terminal PB10 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB10. Supported peripheral buses: General.
24PB11Digital_IOSignal terminal PB11 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB11. Supported peripheral buses: General.
25PB12Digital_IOSignal terminal PB12 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB12. Supported peripheral buses: General.
26PB13Digital_IOSignal terminal PB13 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB13. Supported peripheral buses: General.
27PB14Digital_IOSignal terminal PB14 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB14. Supported peripheral buses: General.
28PB15Digital_IOSignal terminal PB15 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB15. Supported peripheral buses: General.
29PA12Digital_IOSignal terminal PA12 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
30PA13Digital_IOSignal terminal PA13 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
31PA14Digital_IOSignal terminal PA14 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
32PA15Digital_IOSignal terminal PA15 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
33GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
34VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 2.7V – 5.5V domain (Max rating: 5.5V).
35PA16Digital_IOSignal terminal PA16 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA16. Supported peripheral buses: General.
36PA17Digital_IOSignal terminal PA17 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA17. Supported peripheral buses: General.
37PA18Digital_IOSignal terminal PA18 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA18. Supported peripheral buses: General.
38PA19Digital_IOSignal terminal PA19 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA19. Supported peripheral buses: General.
39PB16Digital_IOSignal terminal PB16 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB16. Supported peripheral buses: General.
40PB17Digital_IOSignal terminal PB17 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB17. Supported peripheral buses: General.
41PA20Digital_IOSignal terminal PA20 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA20. Supported peripheral buses: General.
42PA21Digital_IOSignal terminal PA21 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA21. Supported peripheral buses: General.
43PA22Digital_IOSignal terminal PA22 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA22. Supported peripheral buses: General.
44PA23Digital_IOSignal terminal PA23 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA23. Supported peripheral buses: General.
45PA24Digital_IOSignal terminal PA24 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA24. Supported peripheral buses: General.
46PA25Digital_IOSignal terminal PA25 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA25. Supported peripheral buses: General.
47GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
48VDDIOPower_InPrimary positive power supply input (VDDIO) operating in the 2.7V – 5.5V domain (Max rating: 5.5V).
49PB22Digital_IOSignal terminal PB22 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB22. Supported peripheral buses: General.
50PA23Digital_IOSignal terminal PA23 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA23. Supported peripheral buses: General.
51PA27Digital_IOSignal terminal PA27 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA27. Supported peripheral buses: General.
52RESETDigital_IOActive-low hardware reset terminal (RESET): pulling this pin Low resets the processor core and peripherals.
53PA28Digital_IOSignal terminal PA28 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA28. Supported peripheral buses: General.
54GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
55VDDCOREPower_InPrimary positive power supply input (VDDCORE) operating in the 2.7V – 5.5V domain (Max rating: 5.5V).
56VDDINPower_InPrimary positive power supply input (VDDIN) operating in the 2.7V – 5.5V domain (Max rating: 5.5V).
57PA30Digital_IOSignal terminal PA30 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA30. Supported peripheral buses: General.
58PA31Digital_IOSignal terminal PA31 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PA31. Supported peripheral buses: General.
59PB30Digital_IOSignal terminal PB30 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB30. Supported peripheral buses: General.
60PB31Digital_IOSignal terminal PB31 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB31. Supported peripheral buses: General.
61PB00Digital_IOSignal terminal PB00 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB00. Supported peripheral buses: General.
62PB01Digital_IOSignal terminal PB01 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB01. Supported peripheral buses: General.
63PB02Digital_IOSignal terminal PB02 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB02. Supported peripheral buses: General.
64PB03Digital_IOSignal terminal PB03 (I/O, 2.7V – 5.5V domain). Multiplexed alternate functions: PB03. Supported peripheral buses: General.
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