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STM32H7B3VIH6Q (TFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32H7B3VIH6Q

STTFBGA-100 · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32H7B3VIH6Q (TFBGA-100)A1PE6A2PE5A3PE2A4PB8A5BOOT0A6PB5A7PD6A8PD3A9PD2A10PC12B1PC14-OSC32_IB2PC15-OSC32_OB3PE3B4PE0B5PB7B6PB3B7PD4B8PD1B9PC11B10PC10C1VSSC2VBATC3PE4C4PE1C5PB4C6PD7C7PD0C8PA15C9PA14C10PA13D1VSSSMPSD2VLXSMPSD3PDR_OND4PB6D5VSSD6VDDD7PD5D8VCAPD9PA12D10PA11E1VDDSMPSE2VFBSMPSE3PB9E4PC13E5VDDE6VDDLDOE7VSSE8VDD33USBE9PA9E10PA10K10PB15K9PB14K8PB12K7PB10K6PE9K5PB1K4PB0K3PA7K2PA5K1PA4J10PD10J9PD8J8PB13J7PB11J6PE8J5PB2J4PC5J3PA6J2PA1J1VREF+H10PD13H9PD12H8PD9H7PD11H6PE10H5PE7H4PC4H3PA2H2VSSAH1VDDAG10PC8G9PC7G8PD15G7PD14G6VCAPG5PA3G4PC3_CG3PA0G2PH1- OSC_OUTG1PH0- OSC_INF10PA8F9PC9F8PC6F7VDD50USBF6VDDF5VSSF4PC2_CF3PC0F2NRSTF1PC1Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=8.00mm · Pitch e=0.80mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PE6I/OMultiplexed I/O & Peripheral Pin PE6 (General)
A2PE5I/OMultiplexed I/O & Peripheral Pin PE5 (General)
A3PE2I/OMultiplexed I/O & Peripheral Pin PE2 (General)
A4PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
A5BOOT0IInput-Only Pin BOOT0 (General)
A6PB5I/OMultiplexed I/O & Peripheral Pin PB5 (General)
A7PD6I/OMultiplexed I/O & Peripheral Pin PD6 (General)
A8PD3I/OMultiplexed I/O & Peripheral Pin PD3 (General)
A9PD2I/OMultiplexed I/O & Peripheral Pin PD2 (General)
A10PC12I/OMultiplexed I/O & Peripheral Pin PC12 (General)
B1PC14-OSC32_INI/OMultiplexed I/O & Peripheral Pin PC14-OSC32_IN (RTC/CLK)
B2PC15-OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15-OSC32_OUT (RTC/CLK)
B3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
B4PE0I/OMultiplexed I/O & Peripheral Pin PE0 (General)
B5PB7I/OMultiplexed I/O & Peripheral Pin PB7 (General)
B6PB3I/OMultiplexed I/O & Peripheral Pin PB3 (General)
B7PD4I/OMultiplexed I/O & Peripheral Pin PD4 (General)
B8PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
B9PC11I/OMultiplexed I/O & Peripheral Pin PC11 (General)
B10PC10I/OMultiplexed I/O & Peripheral Pin PC10 (General)
C1VSSGNDGround Reference Pin (VSS)
C2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
C3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (General)
C4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (General)
C5PB4I/OMultiplexed I/O & Peripheral Pin PB4 (General)
C6PD7I/OMultiplexed I/O & Peripheral Pin PD7 (General)
C7PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
C8PA15I/OMultiplexed I/O & Peripheral Pin PA15 (General)
C9PA14I/OMultiplexed I/O & Peripheral Pin PA14 (General)
C10PA13I/OMultiplexed I/O & Peripheral Pin PA13 (General)
D1VSSSMPSGNDGround Reference Pin (VSSSMPS)
D2VLXSMPSI/OMultiplexed I/O & Peripheral Pin VLXSMPS (General)
D3PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
D4PB6I/OMultiplexed I/O & Peripheral Pin PB6 (General)
D5VSSGNDGround Reference Pin (VSS)
D6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
D7PD5I/OMultiplexed I/O & Peripheral Pin PD5 (General)
D8VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
D9PA12I/OMultiplexed I/O & Peripheral Pin PA12 (General)
D10PA11I/OMultiplexed I/O & Peripheral Pin PA11 (General)
E1VDDSMPSPowerPower Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V))
E2VFBSMPSI/OMultiplexed I/O & Peripheral Pin VFBSMPS (General)
E3PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
E4PC13I/OMultiplexed I/O & Peripheral Pin PC13 (General)
E5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
E6VDDLDOPowerPower Supply Input (VDDLDO — 3.3V VDD (Max 4.0V))
E7VSSGNDGround Reference Pin (VSS)
E8VDD33USBPowerPower Supply Input (VDD33USB — 3.3V VDD (Max 4.0V))
E9PA9I/OMultiplexed I/O & Peripheral Pin PA9 (General)
E10PA10I/OMultiplexed I/O & Peripheral Pin PA10 (General)
F1PC1I/OMultiplexed I/O & Peripheral Pin PC1 (General)
F2NRSTISystem Enable & Hardware Reset (NRST)
F3PC0I/OMultiplexed I/O & Peripheral Pin PC0 (General)
F4PC2_CI/OMultiplexed I/O & Peripheral Pin PC2_C (General)
F5VSSGNDGround Reference Pin (VSS)
F6VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F7VDD50USBPowerPower Supply Input (VDD50USB — 3.3V VDD (Max 4.0V))
F8PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
F9PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
F10PA8I/OMultiplexed I/O & Peripheral Pin PA8 (General)
G1PH0- OSC_INI/OMultiplexed I/O & Peripheral Pin PH0- OSC_IN (RTC/CLK)
G2PH1- OSC_OUTI/OMultiplexed I/O & Peripheral Pin PH1- OSC_OUT (RTC/CLK)
G3PA0I/OMultiplexed I/O & Peripheral Pin PA0 (General)
G4PC3_CI/OMultiplexed I/O & Peripheral Pin PC3_C (General)
G5PA3I/OMultiplexed I/O & Peripheral Pin PA3 (General)
G6VCAPI/OMultiplexed I/O & Peripheral Pin VCAP (General)
G7PD14I/OMultiplexed I/O & Peripheral Pin PD14 (General)
G8PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
G9PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
G10PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
H1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H2VSSAGNDGround Reference Pin (VSSA)
H3PA2I/OMultiplexed I/O & Peripheral Pin PA2 (General)
H4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (General)
H5PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
H6PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
H7PD11I/OMultiplexed I/O & Peripheral Pin PD11 (General)
H8PD9I/OMultiplexed I/O & Peripheral Pin PD9 (General)
H9PD12I/OMultiplexed I/O & Peripheral Pin PD12 (General)
H10PD13I/OMultiplexed I/O & Peripheral Pin PD13 (General)
J1VREF+AnalogMultiplexed I/O & Peripheral Pin VREF+ (General)
J2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (General)
J3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (General)
J4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (General)
J5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
J6PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
J7PB11I/OMultiplexed I/O & Peripheral Pin PB11 (General)
J8PB13I/OMultiplexed I/O & Peripheral Pin PB13 (General)
J9PD8I/OMultiplexed I/O & Peripheral Pin PD8 (General)
J10PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
K1PA4I/OMultiplexed I/O & Peripheral Pin PA4 (General)
K2PA5I/OMultiplexed I/O & Peripheral Pin PA5 (General)
K3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (General)
K4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (General)
K5PB1I/OMultiplexed I/O & Peripheral Pin PB1 (General)
K6PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
K7PB10I/OMultiplexed I/O & Peripheral Pin PB10 (General)
K8PB12I/OMultiplexed I/O & Peripheral Pin PB12 (General)
K9PB14I/OMultiplexed I/O & Peripheral Pin PB14 (General)
K10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (General)
PIN A1 PE6
I/O
Multiplexed I/O & Peripheral Pin PE6 (General)
Design note: Signal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 22 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32H7B3VIH6Q (ST · TFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32H7B3VIH6Q (TFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32H7B3VIH6Q (TFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32H7B3VIH6Q (TFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32H7B3VIH6Q (TFBGA-100) - 4. Package Dimensions (D×E×A)
TFBGA-100 · 8.00×8.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32H7B3VIH6Q (TFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32H7B3VIH6Q (TFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (22 figures · Page 1/2)
Showing 1–12 of 22 uncropped original figures for STM32H7B3VIH / STM32H7B3ZIT / STM32H7B3NIH
P1 · p01_fig01EXACT PACKAGE
STM32H7B3VIH6Q (TFBGA-100) — WLCSP132 (4.57 X 4.37 mm) | LQFP64 (10 x 10 mm) | LQFP100 (14 x 14 mm) | LQFP144 (20x20 mm) | LQFP176 (24 x 24 mm) | TFBGA100 | (8 x 8 mm) TFBGA216 (13x13 mm) | TFBGA225 (13x13 mm) | FBGA | UFBGA169 | (7 x 7 mm) UFBGA176+25 | (10x10 mm) | F
WLCSP132 (4.57 X 4.37 mm) | LQFP64 (10 x 10 mm) | LQFP100 (14 x 14 mm) | LQFP144 (20x20 mm) | LQFP176 (24 x 24 mm) | TFBGA100 | (8 x 8 mm) TFBGA216 (13x13 mm) | TFBGA225 (13x13 mm) | FBGA | UFBGA169 | (7 x 7 mm) UFBGA176+25 | (10x10 mm) | F
P39 · p39_fig01EXACT PACKAGE
STM32H7B3VIH6Q (TFBGA-100) — Figure 7. TFBGA100 (STM32H7B3xI with SMPS) pinout
Figure 7. TFBGA100 (STM32H7B3xI with SMPS) pinout
P39 · p39_fig02EXACT PACKAGE
STM32H7B3VIH6Q (TFBGA-100) — Figure 8. TFBGA100 (STM32H7B3xI without SMPS) pinout
Figure 8. TFBGA100 (STM32H7B3xI without SMPS) pinout
P191 · p191_fig01EXACT PACKAGE
STM32H7B3VIH6Q (TFBGA-100) — A1 0.150 - - 0.0059 - -
A1 0.150 - - 0.0059 - -
P191 · p191_fig02EXACT PACKAGE
STM32H7B3VIH6Q (TFBGA-100) — Figure 89. TFBGA100 - Recommended footprint
Figure 89. TFBGA100 - Recommended footprint
P36 · p36_fig011726×1381px
STM32H7B3VIH6Q (TFBGA-100) — Figure 4. LQFP64 (STM32H7B3xI without SMPS) pinout
Figure 4. LQFP64 (STM32H7B3xI without SMPS) pinout
P49 · p49_fig011957×901px
STM32H7B3VIH6Q (TFBGA-100) — DFSDM1_DATIN3,
DFSDM1_DATIN3,
P80 · p80_fig011500×2357px
STM32H7B3VIH6Q (TFBGA-100) — Figure 21. Power supply scheme
Figure 21. Power supply scheme
P109 · p109_fig011371×460px
STM32H7B3VIH6Q (TFBGA-100) — Figure 32. Typical application with an 8 MHz crystal
Figure 32. Typical application with an 8 MHz crystal
P190 · p190_fig011569×1068px
STM32H7B3VIH6Q (TFBGA-100) — 1 2 3 4 5 6 7 8 9 10 K | J H G | F E D C B A | A2 | A1 | A | (100 BALLS) b | eee | fff | C A B | C | D | E | F e | B | G e | A1 ball identifier | A1 ball | index area | A | D1 | E1 | BOTTOM VIEW TOP VIEW | 1. Drawing is not to scale
1 2 3 4 5 6 7 8 9 10 K | J H G | F E D C B A | A2 | A1 | A | (100 BALLS) b | eee | fff | C A B | C | D | E | F e | B | G e | A1 ball identifier | A1 ball | index area | A | D1 | E1 | BOTTOM VIEW TOP VIEW | 1. Drawing is not to scale
P41 · p41_fig01EXACT PACKAGE
STM32H7B3VIH6Q (TFBGA-100) — Figure 10. LQFP144 (STM32H7B3xI with SMPS) pinout [LQFP-144(20x20)]
Figure 10. LQFP144 (STM32H7B3xI with SMPS) pinout [LQFP-144(20x20)]
P42 · p42_fig01EXACT PACKAGE
STM32H7B3VIH6Q (TFBGA-100) — Figure 11. LQFP144 (STM32H7B3xI without SMPS) pinout [LQFP-144(20x20)]
Figure 11. LQFP144 (STM32H7B3xI without SMPS) pinout [LQFP-144(20x20)]
Page 1 / 2 (22 extracted figures)

Technical Specifications & Part Details (STM32H7B3VIH6Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32H7B3VIH6Q (TFBGA-100) is a 100-pin embedded microcontroller unit (mcu) featuring a 8.00 × 8.00 × 1.12 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
280 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 1.12 mm (A1=0.25 mm)
Package family: BGA (TFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32H7B3VIH / STM32H7B3ZIT / STM32H7B3NIH (3)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (TFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.12mm · e=0.80mm
Pad Size (W × L)Level B
0.32 × 0.32 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32H7B3VIH6Q (TFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32H7B3VIH6Q (TFBGA-100)?

Manufactured by ST, the STM32H7B3VIH6Q is housed in a TFBGA-100 package with 100 pins and a 0.80 mm lead pitch. Key pins include: A1 (PE6: Multiplexed I/O & Peripheral Pin PE6 (General)), A2 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), A3 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), A4 (PB8: Multiplexed I/O & Peripheral Pin PB8 (General)), A5 (BOOT0: Input-Only Pin BOOT0 (General)), A6 (PB5: Multiplexed I/O & Peripheral Pin PB5 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32H7B3VIH6Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32H7B3VIH6Q (TFBGA-100) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32H7B3VIH6Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32H7B3VIH6Q (ST, TFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32H7B3VIH / STM32H7B3ZIT / STM32H7B3NIH Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General.
A2PE5Digital_IOSignal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General.
A3PE2Digital_IOSignal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General.
A4PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
A5BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
A6PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB5. Supported peripheral buses: General.
A7PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: General.
A8PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: General.
A9PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: General.
A10PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: General.
B1PC14-OSC32_INDigital_IOSignal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK.
B2PC15-OSC32_OUTDigital_IOSignal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK.
B3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
B4PE0Digital_IOSignal terminal PE0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE0. Supported peripheral buses: General.
B5PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: General.
B6PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB3. Supported peripheral buses: General.
B7PD4Digital_IOSignal terminal PD4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD4. Supported peripheral buses: General.
B8PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
B9PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: General.
B10PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: General.
C1VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
C3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General.
C4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: General.
C5PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB4. Supported peripheral buses: General.
C6PD7Digital_IOSignal terminal PD7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD7. Supported peripheral buses: General.
C7PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
C8PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA15. Supported peripheral buses: General.
C9PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: General.
C10PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: General.
D1VSSSMPSGND0V electrical ground return terminal (VSSSMPS) for internal core logic, I/O drivers, and analog sub-blocks.
D2VLXSMPSDigital_IOSignal terminal VLXSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VLXSMPS. Supported peripheral buses: General.
D3PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
D4PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: General.
D5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
D6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
D7PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: General.
D8VCAPDigital_IOSignal terminal VCAP (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP. Supported peripheral buses: General.
D9PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: General.
D10PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: General.
E1VDDSMPSPower_InPrimary positive power supply input (VDDSMPS) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E2VFBSMPSDigital_IOSignal terminal VFBSMPS (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VFBSMPS. Supported peripheral buses: General.
E3PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
E4PC13Digital_IOSignal terminal PC13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: General.
E5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E6VDDLDOPower_InPrimary positive power supply input (VDDLDO) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E7VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E8VDD33USBPower_InPrimary positive power supply input (VDD33USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
E9PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: General.
E10PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: General.
F1PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: General.
F2NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
F3PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: General.
F4PC2_CDigital_IOSignal terminal PC2_C (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2_C. Supported peripheral buses: General.
F5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
F6VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F7VDD50USBPower_InPrimary positive power supply input (VDD50USB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F8PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
F9PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
F10PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: General.
G1PH0- OSC_INDigital_IOSignal terminal PH0- OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH0- OSC_IN. Supported peripheral buses: RTC/CLK.
G2PH1- OSC_OUTDigital_IOSignal terminal PH1- OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PH1- OSC_OUT. Supported peripheral buses: RTC/CLK.
G3PA0Digital_IOSignal terminal PA0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: General.
G4PC3_CDigital_IOSignal terminal PC3_C (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3_C. Supported peripheral buses: General.
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