![STM32L562ZET6Q (LQFP-144(20x20)) — Figure 10. STM32L562xx LQFP48 pinout [LQFP-48(7x7)]](/api/v1/assets/C1236637/extracted/figures/p81_fig01.png)
![STM32L562ZET6Q (LQFP-144(20x20)) — Figure 76. LQFP48 outline [LQFP-48(7x7)]](/api/v1/assets/C1236637/extracted/figures/p310_fig01.png)
LQFP-48(7x7) · 48P
Synchronized Pinout (Symbol / 2D / 3D) (144/144)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | VBAT | Power | Power Supply Input (VBAT — 3.3V VDD (Max 4.0V)) |
| 2 | PC13 | I/O | Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK) |
| 3 | PC14 - OSC3_2IN (PC14) | I/O | Multiplexed I/O & Peripheral Pin PC14 - OSC3_2IN (PC14) (RTC/CLK) |
| 4 | NC | NC | No Connect (Leave Floating) |
| 5 | PH0 - OSC_I N (PH0) | I/O | Multiplexed I/O & Peripheral Pin PH0 - OSC_I N (PH0) (RTC/CLK) |
| 6 | PH1 - OSC_ OUT (PH1) | I/O | Multiplexed I/O & Peripheral Pin PH1 - OSC_ OUT (PH1) (RTC/CLK) |
| 7 | NRST | I | System Enable & Hardware Reset (NRST) |
| 8 | VSSA/ VREF - | GND | Ground Reference Pin (VSSA/ VREF -) |
| 9 | VDDA/ VREF + | Power | Power Supply Input (VDDA/ VREF + — 3.3V VDD (Max 4.0V)) |
| 10 | PA0 | I/O | Multiplexed I/O & Peripheral Pin PA0 (UART, SPI, ADC, PWM) |
| 11 | PA1 | I/O | Multiplexed I/O & Peripheral Pin PA1 (UART, SPI, I2C, ADC, PWM) |
| 12 | PA2 | I/O | Multiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM) |
| 13 | PA3 | I/O | Multiplexed I/O & Peripheral Pin PA3 (UART, ADC, PWM) |
| 14 | PA4 | I/O | Multiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC) |
| 15 | PA5 | I/O | Multiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC, PWM) |
| 16 | PA6 | I/O | Multiplexed I/O & Peripheral Pin PA6 (UART, SPI, ADC, PWM) |
| 17 | PA7 | I/O | Multiplexed I/O & Peripheral Pin PA7 (SPI, I2C, ADC, PWM) |
| 18 | PB0 | I/O | Multiplexed I/O & Peripheral Pin PB0 (UART, SPI, ADC, PWM) |
| 19 | PB1 | I/O | Multiplexed I/O & Peripheral Pin PB1 (UART, ADC, PWM) |
| 20 | PB2 | I/O | Multiplexed I/O & Peripheral Pin PB2 (I2C, RTC/CLK) |
| 21 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (UART, SPI, I2C, PWM) |
| 22 | VDD12_1 | Power | Power Supply Input (VDD12_1 — 3.3V VDD (Max 4.0V)) |
| 23 | VSS | GND | Ground Reference Pin (VSS) |
| 24 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 25 | PB12 | I/O | Multiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C) |
| 26 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (UART, SPI, I2C, PWM) |
| 27 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (UART, SPI, I2C, PWM) |
| 28 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (SPI, I2C, PWM, RTC/CLK) |
| 29 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (UART, SPI, RTC/CLK) |
| 30 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (UART, PWM) |
| 31 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (UART, I2C, PWM) |
| 32 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (USB, UART, SPI, PWM) |
| 33 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (USB, UART, SPI) |
| 34 | PA13 (JTMS/ SWDI O) | I/O | Multiplexed I/O & Peripheral Pin PA13 (JTMS/ SWDI O) (SWD/JTAG) |
| 35 | VSS | GND | Ground Reference Pin (VSS) |
| 36 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 37 | PA14 (JTCK/ SWCL K) | I/O | Multiplexed I/O & Peripheral Pin PA14 (JTCK/ SWCL K) (I2C, SWD/JTAG) |
| 38 | PA15 (JTDI) | I/O | Multiplexed I/O & Peripheral Pin PA15 (JTDI) (UART, SPI, SWD/JTAG) |
| 39 | PB3 (JTDO/ TRAC ESWO ) | I/O | Multiplexed I/O & Peripheral Pin PB3 (JTDO/ TRAC ESWO ) (UART, SPI, PWM, SWD/JTAG) |
| 40 | PB4 (NJTR ST) | I/O | Multiplexed I/O & Peripheral Pin PB4 (NJTR ST) (UART, SPI, I2C, SWD/JTAG) |
| 41 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (UART, SPI, I2C, PWM) |
| 42 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (UART, I2C, PWM) |
| 43 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (UART, I2C, PWM) |
| 44 | PH3 - BOOT 0 | I/O | Multiplexed I/O & Peripheral Pin PH3 - BOOT 0 (General) |
| 45 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (I2C, PWM) |
| 46 | VDD12_2 | Power | Power Supply Input (VDD12_2 — 3.3V VDD (Max 4.0V)) |
| 47 | VSS | GND | Ground Reference Pin (VSS) |
| 48 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 49 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 50 | PF13 | I/O | Multiplexed I/O & Peripheral Pin PF13 (General) |
| 51 | PF14 | I/O | Multiplexed I/O & Peripheral Pin PF14 (General) |
| 52 | PC11 | I/O | Multiplexed I/O & Peripheral Pin PC11 (UART, SPI) |
| 53 | PC12 | I/O | Multiplexed I/O & Peripheral Pin PC12 (UART, SPI) |
| 54 | PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 (UART) |
| 55 | PE7 | I/O | Multiplexed I/O & Peripheral Pin PE7 (General) |
| 56 | PE8 | I/O | Multiplexed I/O & Peripheral Pin PE8 (General) |
| 57 | PD10 | I/O | Multiplexed I/O & Peripheral Pin PD10 (UART, SPI) |
| 58 | PD11 | I/O | Multiplexed I/O & Peripheral Pin PD11 (UART, SPI, I2C) |
| 59 | PD12 | I/O | Multiplexed I/O & Peripheral Pin PD12 (UART, PWM) |
| 60 | PD13 | I/O | Multiplexed I/O & Peripheral Pin PD13 (PWM) |
| 61 | PD14 | I/O | Multiplexed I/O & Peripheral Pin PD14 (PWM) |
| 62 | PD15 | I/O | Multiplexed I/O & Peripheral Pin PD15 (PWM) |
| 63 | PE13 | I/O | Multiplexed I/O & Peripheral Pin PE13 (General) |
| 64 | PE14 | I/O | Multiplexed I/O & Peripheral Pin PE14 (General) |
| 65 | PE15 | I/O | Multiplexed I/O & Peripheral Pin PE15 (General) |
| 66 | PB10 | I/O | Multiplexed I/O & Peripheral Pin PB10 (General) |
| 67 | PB11 | I/O | Multiplexed I/O & Peripheral Pin PB11 (General) |
| 68 | VDDSMPS | Power | Power Supply Input (VDDSMPS — 3.3V VDD (Max 4.0V)) |
| 69 | VLXSMPS | I/O | Multiplexed I/O & Peripheral Pin VLXSMPS (General) |
| 70 | VSSSMPS | GND | Ground Reference Pin (VSSSMPS) |
| 71 | VSS | GND | Ground Reference Pin (VSS) |
| 72 | V15SMPS_1 | I/O | Multiplexed I/O & Peripheral Pin V15SMPS_1 (General) |
| 73 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 74 | PB13 | I/O | Multiplexed I/O & Peripheral Pin PB13 (General) |
| 75 | PB14 | I/O | Multiplexed I/O & Peripheral Pin PB14 (General) |
| 76 | PB15 | I/O | Multiplexed I/O & Peripheral Pin PB15 (General) |
| 77 | PD8 | I/O | Multiplexed I/O & Peripheral Pin PD8 (General) |
| 78 | PD9 | I/O | Multiplexed I/O & Peripheral Pin PD9 (General) |
| 79 | PD10 | I/O | Multiplexed I/O & Peripheral Pin PD10 (General) |
| 80 | PD11 | I/O | Multiplexed I/O & Peripheral Pin PD11 (General) |
| 81 | PD12 | I/O | Multiplexed I/O & Peripheral Pin PD12 (General) |
| 82 | PD13 | I/O | Multiplexed I/O & Peripheral Pin PD13 (General) |
| 83 | VSS | GND | Ground Reference Pin (VSS) |
| 84 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 85 | PD14 | I/O | Multiplexed I/O & Peripheral Pin PD14 (General) |
| 86 | PD15 | I/O | Multiplexed I/O & Peripheral Pin PD15 (General) |
| 87 | PD6 | I/O | Multiplexed I/O & Peripheral Pin PD6 (UART, I2C) |
| 88 | PD7 | I/O | Multiplexed I/O & Peripheral Pin PD7 (UART) |
| 89 | PG4 | I/O | Multiplexed I/O & Peripheral Pin PG4 (General) |
| 90 | PG5 | I/O | Multiplexed I/O & Peripheral Pin PG5 (General) |
| 91 | PG6 | I/O | Multiplexed I/O & Peripheral Pin PG6 (UART, I2C) |
| 92 | PG7 | I/O | Multiplexed I/O & Peripheral Pin PG7 (General) |
| 93 | PG8 | I/O | Multiplexed I/O & Peripheral Pin PG8 (I2C) |
| 94 | VSS | GND | Ground Reference Pin (VSS) |
| 95 | VDDIO 2 | Power | Power Supply Input (VDDIO 2 — 3.3V VDD (Max 4.0V)) |
| 96 | PC6 | I/O | Multiplexed I/O & Peripheral Pin PC6 (General) |
| 97 | PC7 | I/O | Multiplexed I/O & Peripheral Pin PC7 (General) |
| 98 | PC8 | I/O | Multiplexed I/O & Peripheral Pin PC8 (General) |
| 99 | PC9 | I/O | Multiplexed I/O & Peripheral Pin PC9 (General) |
| 100 | PA8 | I/O | Multiplexed I/O & Peripheral Pin PA8 (General) |
| 101 | PA9 | I/O | Multiplexed I/O & Peripheral Pin PA9 (General) |
| 102 | PA10 | I/O | Multiplexed I/O & Peripheral Pin PA10 (General) |
| 103 | PA11 | I/O | Multiplexed I/O & Peripheral Pin PA11 (General) |
| 104 | PA12 | I/O | Multiplexed I/O & Peripheral Pin PA12 (General) |
| 105 | PA13 | I/O | Multiplexed I/O & Peripheral Pin PA13 (General) |
| 106 | VDDUSB | Power | Power Supply Input (VDDUSB — 3.3V VDD (Max 4.0V)) |
| 107 | VSS | GND | Ground Reference Pin (VSS) |
| 108 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 109 | PA14 | I/O | Multiplexed I/O & Peripheral Pin PA14 (General) |
| 110 | PA15 | I/O | Multiplexed I/O & Peripheral Pin PA15 (General) |
| 111 | PC10 | I/O | Multiplexed I/O & Peripheral Pin PC10 (General) |
| 112 | PC11 | I/O | Multiplexed I/O & Peripheral Pin PC11 (General) |
| 113 | PC12 | I/O | Multiplexed I/O & Peripheral Pin PC12 (General) |
| 114 | PD0 | I/O | Multiplexed I/O & Peripheral Pin PD0 (General) |
| 115 | PD1 | I/O | Multiplexed I/O & Peripheral Pin PD1 (General) |
| 116 | PD2 | I/O | Multiplexed I/O & Peripheral Pin PD2 (General) |
| 117 | PD3 | I/O | Multiplexed I/O & Peripheral Pin PD3 (General) |
| 118 | PD4 | I/O | Multiplexed I/O & Peripheral Pin PD4 (General) |
| 119 | PD5 | I/O | Multiplexed I/O & Peripheral Pin PD5 (General) |
| 120 | VSS | GND | Ground Reference Pin (VSS) |
| 121 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
| 122 | PD6 | I/O | Multiplexed I/O & Peripheral Pin PD6 (General) |
| 123 | PD7 | I/O | Multiplexed I/O & Peripheral Pin PD7 (General) |
| 124 | PG9 | I/O | Multiplexed I/O & Peripheral Pin PG9 (General) |
| 125 | PG10 | I/O | Multiplexed I/O & Peripheral Pin PG10 (General) |
| 126 | PG12 | I/O | Multiplexed I/O & Peripheral Pin PG12 (UART, SPI, I2C) |
| 127 | PG13 | I/O | Multiplexed I/O & Peripheral Pin PG13 (UART, I2C) |
| 128 | PG14 | I/O | Multiplexed I/O & Peripheral Pin PG14 (I2C) |
| 129 | VSS | GND | Ground Reference Pin (VSS) |
| 130 | VDDIO 2 | Power | Power Supply Input (VDDIO 2 — 3.3V VDD (Max 4.0V)) |
| 131 | PG15 | I/O | Multiplexed I/O & Peripheral Pin PG15 (General) |
| 132 | PB3 | I/O | Multiplexed I/O & Peripheral Pin PB3 (General) |
| 133 | PB4 | I/O | Multiplexed I/O & Peripheral Pin PB4 (General) |
| 134 | PB5 | I/O | Multiplexed I/O & Peripheral Pin PB5 (General) |
| 135 | PB6 | I/O | Multiplexed I/O & Peripheral Pin PB6 (General) |
| 136 | PB7 | I/O | Multiplexed I/O & Peripheral Pin PB7 (General) |
| 137 | PH3-BOOT0 | I/O | Multiplexed I/O & Peripheral Pin PH3-BOOT0 (General) |
| 138 | PB8 | I/O | Multiplexed I/O & Peripheral Pin PB8 (General) |
| 139 | PB9 | I/O | Multiplexed I/O & Peripheral Pin PB9 (General) |
| 140 | PE0 | I/O | Multiplexed I/O & Peripheral Pin PE0 (General) |
| 141 | PE1 | I/O | Multiplexed I/O & Peripheral Pin PE1 (General) |
| 142 | VSS | GND | Ground Reference Pin (VSS) |
| 143 | V15SMPS_2 | I/O | Multiplexed I/O & Peripheral Pin V15SMPS_2 (General) |
| 144 | VDD | Power | Power Supply Input (VDD — 3.3V VDD (Max 4.0V)) |
PIN 1 VBAT
PowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 30 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (144 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-144(20x20) · 20.00×20.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (144 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (30 figures · Page 1/3)
Showing 1–12 of 30 uncropped original figures for STM32L562
P88 · p88_fig01EXACT PACKAGE
P89 · p89_fig01EXACT PACKAGE
P330 · p330_fig01EXACT PACKAGE
P1 · p01_fig011751×860px
P141 · p141_fig011560×1866px
P218 · p218_fig011546×702px
P219 · p219_fig011546×702px
P321 · p321_fig011560×845px
P326 · p326_fig011698×534px
P326 · p326_fig021546×1534px
P81 · p81_fig01EXACT PACKAGE
P310 · p310_fig01EXACT PACKAGE
Page 1 / 3 (30 extracted figures)
Technical Specifications & Part Details (STM32L562ZET6Q)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:STM32L562ZET6Q (LQFP-144(20x20)) is a 144-pin embedded microcontroller unit (mcu) featuring a 20.00 × 20.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.71 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
1.71 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
110 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
49 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
20.00 × 20.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-144(20x20))
Pin Count & Lead PitchN / e
144 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, I2C, ADC, DAC, JTAG / SWD, IrDA, PWM, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PH3-BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol144 auto-grouped pins
IPC-7351B Land Pattern144 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — STM32L562 (11)
UFQFPN-48(7x7) · 49P
UFQFPN-48(7x7) · 49P
LQFP-64(10x10) · 64P
LQFP-64(10x10) · 64P
WLCSP-81(4.1x4.4) · 81P
UFBGA-132(7x7x0.5) · 132P
UFBGA-132(7x7x0.5) · 132P
LQFP-144(20x20) · 144P
LQFP-144(20x20) · 144P
LQFP-144(20x20) · 144P
Mechanical Dimensions & Land Pattern (LQFP-144(20x20))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
20.00 × 20.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.35 × 1.35 mm
Pins / Total PadsTopology
144P / 144Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-144(20x20) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32L562ZET6Q (LQFP-144(20x20))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32L562ZET6Q (LQFP-144(20x20))?
Manufactured by ST, the STM32L562ZET6Q is housed in a LQFP-144(20x20) package with 144 pins and a 0.50 mm lead pitch, supporting a VCC supply range of 1.71 V to 3.6 V. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13: Multiplexed I/O & Peripheral Pin PC13 (RTC/CLK)), 3 (PC14 - OSC3_2IN (PC14): Multiplexed I/O & Peripheral Pin PC14 - OSC3_2IN (PC14) (RTC/CLK)), 4 (NC: No Connect (Leave Floating)), 5 (PH0 - OSC_I N (PH0): Multiplexed I/O & Peripheral Pin PH0 - OSC_I N (PH0) (RTC/CLK)), 6 (PH1 - OSC_ OUT (PH1): Multiplexed I/O & Peripheral Pin PH1 - OSC_ OUT (PH1) (RTC/CLK)).
What are the IPC-7351B PCB Footprint dimensions for STM32L562ZET6Q?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32L562ZET6Q (LQFP-144(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32L562ZET6Q?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32L562ZET6Q (ST, LQFP-144(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (144 pins) & STM32L562 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 2 | PC13 | Digital_IO | Signal terminal PC13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC13. Supported peripheral buses: RTC/CLK. |
| 3 | PC14 - OSC3_2IN (PC14) | Digital_IO | Signal terminal PC14 - OSC3_2IN (PC14) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC14 - OSC3_2IN (PC14). Supported peripheral buses: RTC/CLK. |
| 4 | NC | No_Connect | No Connect (Leave Floating) |
| 5 | PH0 - OSC_I N (PH0) | Digital_IO | Signal terminal PH0 - OSC_I N (PH0) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0 - OSC_I N (PH0). Supported peripheral buses: RTC/CLK. |
| 6 | PH1 - OSC_ OUT (PH1) | Digital_IO | Signal terminal PH1 - OSC_ OUT (PH1) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH1 - OSC_ OUT (PH1). Supported peripheral buses: RTC/CLK. |
| 7 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 8 | VSSA/ VREF - | GND | 0V electrical ground return terminal (VSSA/ VREF -) for internal core logic, I/O drivers, and analog sub-blocks. |
| 9 | VDDA/ VREF + | Power_In | Primary positive power supply input (VDDA/ VREF +) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 10 | PA0 | Digital_IO | Signal terminal PA0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 11 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_SCK. Supported peripheral buses: UART, SPI, I2C, ADC, PWM. |
| 12 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM. |
| 13 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC, PWM. |
| 14 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, ADC, DAC. |
| 15 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC, PWM. |
| 16 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 17 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SCL, SPI1_MOSI. Supported peripheral buses: SPI, I2C, ADC, PWM. |
| 18 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, PWM. |
| 19 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: UART, ADC, PWM. |
| 20 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SMBA. Supported peripheral buses: I2C, RTC/CLK. |
| 21 | PB10 | Digital_IO | Signal terminal PB10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 22 | VDD12_1 | Power_In | Primary positive power supply input (VDD12_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 23 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 25 | PB12 | Digital_IO | Signal terminal PB12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SMBA, SPI2_NSS. Supported peripheral buses: UART, SPI, I2C. |
| 26 | PB13 | Digital_IO | Signal terminal PB13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB13. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 27 | PB14 | Digital_IO | Signal terminal PB14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C2_SDA, SPI2_MISO. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 28 | PB15 | Digital_IO | Signal terminal PB15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI, I2C, PWM, RTC/CLK. |
| 29 | PA8 | Digital_IO | Signal terminal PA8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, SPI, RTC/CLK. |
| 30 | PA9 | Digital_IO | Signal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, PWM. |
| 31 | PA10 | Digital_IO | Signal terminal PA10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART, I2C, PWM. |
| 32 | PA11 | Digital_IO | Signal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: USB, UART, SPI, PWM. |
| 33 | PA12 | Digital_IO | Signal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: USB, UART, SPI. |
| 34 | PA13 (JTMS/ SWDI O) | Digital_IO | Signal terminal PA13 (JTMS/ SWDI O) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA13 (JTMS/ SWDI O). Supported peripheral buses: SWD/JTAG. |
| 35 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 36 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 37 | PA14 (JTCK/ SWCL K) | Digital_IO | Signal terminal PA14 (JTCK/ SWCL K) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, I2C4_SMBA. Supported peripheral buses: I2C, SWD/JTAG. |
| 38 | PA15 (JTDI) | Digital_IO | Signal terminal PA15 (JTDI) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_NSSSPI3NSS. Supported peripheral buses: UART, SPI, SWD/JTAG. |
| 39 | PB3 (JTDO/ TRAC ESWO ) | Digital_IO | Signal terminal PB3 (JTDO/ TRAC ESWO ) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI, PWM, SWD/JTAG. |
| 40 | PB4 (NJTR ST) | Digital_IO | Signal terminal PB4 (NJTR ST) (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C3_SDA, SPI1_MISO, SPI3_MISO. Supported peripheral buses: UART, SPI, I2C, SWD/JTAG. |
| 41 | PB5 | Digital_IO | Signal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SMBA, SPI1_MOSI, SPI3_MOSI. Supported peripheral buses: UART, SPI, I2C, PWM. |
| 42 | PB6 | Digital_IO | Signal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB6. Supported peripheral buses: UART, I2C, PWM. |
| 43 | PB7 | Digital_IO | Signal terminal PB7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PB7. Supported peripheral buses: UART, I2C, PWM. |
| 44 | PH3 - BOOT 0 | Digital_IO | Signal terminal PH3 - BOOT 0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH3 - BOOT 0. Supported peripheral buses: General. |
| 45 | PB8 | Digital_IO | Signal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C, PWM. |
| 46 | VDD12_2 | Power_In | Primary positive power supply input (VDD12_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 47 | VSS | GND | 0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks. |
| 48 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 49 | VDD | Power_In | Primary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 50 | PF13 | Digital_IO | Signal terminal PF13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF13. Supported peripheral buses: General. |
| 51 | PF14 | Digital_IO | Signal terminal PF14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF14. Supported peripheral buses: General. |
| 52 | PC11 | Digital_IO | Signal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: UART, SPI. |
| 53 | PC12 | Digital_IO | Signal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MOSI. Supported peripheral buses: UART, SPI. |
| 54 | PD2 | Digital_IO | Signal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART. |
| 55 | PE7 | Digital_IO | Signal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General. |
| 56 | PE8 | Digital_IO | Signal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General. |
| 57 | PD10 | Digital_IO | Signal terminal PD10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD10. Supported peripheral buses: UART, SPI. |
| 58 | PD11 | Digital_IO | Signal terminal PD11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C4_SMBA. Supported peripheral buses: UART, SPI, I2C. |
| 59 | PD12 | Digital_IO | Signal terminal PD12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD12. Supported peripheral buses: UART, PWM. |
| 60 | PD13 | Digital_IO | Signal terminal PD13 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD13. Supported peripheral buses: PWM. |
| 61 | PD14 | Digital_IO | Signal terminal PD14 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD14. Supported peripheral buses: PWM. |
| 62 | PD15 | Digital_IO | Signal terminal PD15 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: PWM. |
| 63 | PE13 | Digital_IO | Signal terminal PE13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: General. |
| 64 | PE14 | Digital_IO | Signal terminal PE14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE14. Supported peripheral buses: General. |