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STM32F765VIH6 (TFBGA-100) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F765VIH6

STID: C1235426TFBGA-100 · 100 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F765VIH6 (TFBGA-100)A1PF1A2PF2A3PF3A4PF4A5PF5A6PF12A7PF13A8PF14A9PF15A10PG0B1PC15- OSC32_B2VBATB3PE3B4PB8B5PB6B6PD5B7PD2B8PC11B9PC10B10PA12C1PH0- OSC_INC2VSSC3PE4C4PE1C5PB5C6PD6C7PD3C8PC12C9PA9C10PA11D1PD15D2PD0D3PD1D4PE7D5PE8D6PE9D7PE10D8PE11D9PE12D10PE13E1NRSTE2PC2E3PE6E4VSSE5VSSE6BYPASS_REGE7VCAP_2E8PD1E9PC9E10PC7K10VSSK9VSSK8VSSK7VSSK6VSSK5PE9K4PB1K3PA7K2PA3K1VDDJ10VSSJ9VSSJ8VSSJ7VSSJ6PE12J5PE8J4PB0J3PA6J2PA2J1VSSH10PB14H9PD10H8PD14H7PE15H6PE11H5PE7H4PC5H3PA5H2PA1H1VDDAG10PB15G9PD11G8PD15G7PE14G6PE10G5PB2G4PC4G3PA4G2PA0- WKUPG1VSSAF10PC6F9PC8F8VCAP_1F7PDR_ONF6VDDUSBF5VDDF4VDDF3PC3F2PC1F1PC0Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.868.663.558.453.348.343.238.133.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0-38.1-43.2-48.3-53.3-58.4-63.5-68.6mm
2. 2D FOOTPRINT
A1B1C1D1E1F1G1H1J1K1A2B2C2D2E2F2G2H2J2K2A3B3C3D3E3F3G3H3J3K3A4B4C4D4E4F4G4H4J4K4A5B5C5D5E5F5G5H5J5K5A6B6C6D6E6F6G6H6J6K6A7B7C7D7E7F7G7H7J7K7A8B8C8D8E8F8G8H8J8K8A9B9C9D9E9F9G9H9J9K9A10B10C10D10E10F10G10H10J10K10E=8.00mm · Pitch e=0.80mmD=8.00mm-6-5-4-3-2-101234566543210-1-2-3-4-5-6mm
3. 3D CAD MODEL
Package Body: 8.00mm × 8.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (100/100)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
A1PF1I/OMultiplexed I/O & Peripheral Pin PF1 (General)
A2PF2I/OMultiplexed I/O & Peripheral Pin PF2 (General)
A3PF3I/OMultiplexed I/O & Peripheral Pin PF3 (General)
A4PF4I/OMultiplexed I/O & Peripheral Pin PF4 (General)
A5PF5I/OMultiplexed I/O & Peripheral Pin PF5 (General)
A6PF12I/OMultiplexed I/O & Peripheral Pin PF12 (General)
A7PF13I/OMultiplexed I/O & Peripheral Pin PF13 (General)
A8PF14I/OMultiplexed I/O & Peripheral Pin PF14 (General)
A9PF15I/OMultiplexed I/O & Peripheral Pin PF15 (General)
A10PG0I/OMultiplexed I/O & Peripheral Pin PG0 (General)
B1PC15- OSC32_OUTI/OMultiplexed I/O & Peripheral Pin PC15- OSC32_OUT (RTC/CLK)
B2VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
B3PE3I/OMultiplexed I/O & Peripheral Pin PE3 (General)
B4PB8I/OMultiplexed I/O & Peripheral Pin PB8 (UART, I2C, CAN)
B5PB6I/OMultiplexed I/O & Peripheral Pin PB6 (UART, I2C)
B6PD5I/OMultiplexed I/O & Peripheral Pin PD5 (UART)
B7PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
B8PC11I/OMultiplexed I/O & Peripheral Pin PC11 (SPI)
B9PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART, SPI)
B10PA12I/OMultiplexed I/O & Peripheral Pin PA12 (UART, SPI, CAN)
C1PH0- OSC_INI/OMultiplexed I/O & Peripheral Pin PH0- OSC_IN (RTC/CLK)
C2VSSGNDGround Reference Pin (VSS)
C3PE4I/OMultiplexed I/O & Peripheral Pin PE4 (SPI)
C4PE1I/OMultiplexed I/O & Peripheral Pin PE1 (UART)
C5PB5I/OMultiplexed I/O & Peripheral Pin PB5 (UART, SPI, CAN)
C6PD6I/OMultiplexed I/O & Peripheral Pin PD6 (UART)
C7PD3I/OMultiplexed I/O & Peripheral Pin PD3 (UART)
C8PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART, SPI)
C9PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART, I2C)
C10PA11I/OMultiplexed I/O & Peripheral Pin PA11 (UART, SPI, PWM)
D1PD15I/OMultiplexed I/O & Peripheral Pin PD15 (General)
D2PD0I/OMultiplexed I/O & Peripheral Pin PD0 (General)
D3PD1I/OMultiplexed I/O & Peripheral Pin PD1 (General)
D4PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
D5PE8I/OMultiplexed I/O & Peripheral Pin PE8 (General)
D6PE9I/OMultiplexed I/O & Peripheral Pin PE9 (General)
D7PE10I/OMultiplexed I/O & Peripheral Pin PE10 (General)
D8PE11I/OMultiplexed I/O & Peripheral Pin PE11 (General)
D9PE12I/OMultiplexed I/O & Peripheral Pin PE12 (General)
D10PE13I/OMultiplexed I/O & Peripheral Pin PE13 (General)
E1NRSTISystem Enable & Hardware Reset (NRST)
E2PC2I/OMultiplexed I/O & Peripheral Pin PC2 (SPI, ADC)
E3PE6I/OMultiplexed I/O & Peripheral Pin PE6 (SPI)
E4VSSGNDGround Reference Pin (VSS)
E5VSSGNDGround Reference Pin (VSS)
E6BYPASS_REGI/OMultiplexed I/O & Peripheral Pin BYPASS_REG (General)
E7VCAP_2I/OMultiplexed I/O & Peripheral Pin VCAP_2 (General)
E8PD1I/OMultiplexed I/O & Peripheral Pin PD1 (UART)
E9PC9I/OMultiplexed I/O & Peripheral Pin PC9 (I2C, RTC/CLK)
E10PC7I/OMultiplexed I/O & Peripheral Pin PC7 (PWM)
F1PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
F2PC1I/OMultiplexed I/O & Peripheral Pin PC1 (SPI, I2C, ADC, RTC/CLK)
F3PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
F4VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F5VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
F6VDDUSBPowerPower Supply Input (VDDUSB — 3.3V VDD (Max 4.0V))
F7PDR_ONI/OMultiplexed I/O & Peripheral Pin PDR_ON (General)
F8VCAP_1I/OMultiplexed I/O & Peripheral Pin VCAP_1 (General)
F9PC8I/OMultiplexed I/O & Peripheral Pin PC8 (UART)
F10PC6I/OMultiplexed I/O & Peripheral Pin PC6 (PWM)
G1VSSAGNDGround Reference Pin (VSSA)
G2PA0- WKUPI/OMultiplexed I/O & Peripheral Pin PA0- WKUP (UART, ADC)
G3PA4I/OMultiplexed I/O & Peripheral Pin PA4 (UART, SPI, ADC, DAC)
G4PC4I/OMultiplexed I/O & Peripheral Pin PC4 (UART, ADC)
G5PB2I/OMultiplexed I/O & Peripheral Pin PB2 (SPI, I2C)
G6PE10I/OMultiplexed I/O & Peripheral Pin PE10 (PWM)
G7PE14I/OMultiplexed I/O & Peripheral Pin PE14 (SPI)
G8PD15I/OMultiplexed I/O & Peripheral Pin PD15 (UART)
G9PD11I/OMultiplexed I/O & Peripheral Pin PD11 (UART, I2C)
G10PB15I/OMultiplexed I/O & Peripheral Pin PB15 (UART, RTC/CLK)
H1VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
H2PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
H3PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, ADC, DAC)
H4PC5I/OMultiplexed I/O & Peripheral Pin PC5 (UART, ADC)
H5PE7I/OMultiplexed I/O & Peripheral Pin PE7 (General)
H6PE11I/OMultiplexed I/O & Peripheral Pin PE11 (SPI)
H7PE15I/OMultiplexed I/O & Peripheral Pin PE15 (General)
H8PD14I/OMultiplexed I/O & Peripheral Pin PD14 (UART)
H9PD10I/OMultiplexed I/O & Peripheral Pin PD10 (General)
H10PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI)
J1VSSGNDGround Reference Pin (VSS)
J2PA2I/OMultiplexed I/O & Peripheral Pin PA2 (SPI, ADC)
J3PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
J4PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
J5PE8I/OMultiplexed I/O & Peripheral Pin PE8 (PWM)
J6PE12I/OMultiplexed I/O & Peripheral Pin PE12 (SPI)
J7VSSGNDGround Reference Pin (VSS)
J8VSSGNDGround Reference Pin (VSS)
J9VSSGNDGround Reference Pin (VSS)
J10VSSGNDGround Reference Pin (VSS)
K1VDDPowerPower Supply Input (VDD — 3.3V VDD (Max 4.0V))
K2PA3I/OMultiplexed I/O & Peripheral Pin PA3 (ADC)
K3PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC, PWM)
K4PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
K5PE9I/OMultiplexed I/O & Peripheral Pin PE9 (UART, PWM)
K6VSSGNDGround Reference Pin (VSS)
K7VSSGNDGround Reference Pin (VSS)
K8VSSGNDGround Reference Pin (VSS)
K9VSSGNDGround Reference Pin (VSS)
K10VSSGNDGround Reference Pin (VSS)
PIN A1 PF1
I/O
Multiplexed I/O & Peripheral Pin PF1 (General)
Design note: Signal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 32 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F765VIH6 (ST · TFBGA-100)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F765VIH6 (TFBGA-100) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F765VIH6 (TFBGA-100) - 2. Standard Pinout (Top View)
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F765VIH6 (TFBGA-100) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F765VIH6 (TFBGA-100) - 4. Package Dimensions (D×E×A)
TFBGA-100 · 8.00×8.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F765VIH6 (TFBGA-100) - 5. Recommended Land Pattern
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F765VIH6 (TFBGA-100) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (32 figures · Page 1/3)
Showing 1–12 of 32 uncropped original figures for STM32F765 / STM32F767 / STM32F769
P56 · p56_fig01EXACT PACKAGE
STM32F765VIH6 (TFBGA-100) — Figure 12. STM32F76xxx TFBGA100 pinout
Figure 12. STM32F76xxx TFBGA100 pinout
P222 · p222_fig01EXACT PACKAGE
STM32F765VIH6 (TFBGA-100) — Figure 86. TFBGA100 outline
Figure 86. TFBGA100 outline
P223 · p223_fig01EXACT PACKAGE
STM32F765VIH6 (TFBGA-100) — Figure 87. TFBGA100 recommended footprint
Figure 87. TFBGA100 recommended footprint
P223 · p223_fig02EXACT PACKAGE
STM32F765VIH6 (TFBGA-100) — Figure 87. TFBGA100 recommended footprint
Figure 87. TFBGA100 recommended footprint
P224 · p224_fig01EXACT PACKAGE
STM32F765VIH6 (TFBGA-100) — Figure 88. TFBGA100 top view example
Figure 88. TFBGA100 top view example
P1 · p01_fig01881×617px
STM32F765VIH6 (TFBGA-100) — • Low-power - Sleep, Stop and Standby modes - VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes backup SRAM
• Low-power - Sleep, Stop and Standby modes - VBAT supply for RTC, 32×32 bit backup registers + 4 Kbytes backup SRAM
P55 · p55_fig011546×1389px
STM32F765VIH6 (TFBGA-100) — Figure 11. STM32F76xxx LQFP100 pinout
Figure 11. STM32F76xxx LQFP100 pinout
P56 · p56_fig01P56
STM32F765VIH6 (TFBGA-100) — Datasheet Page 56 (p56_fig01)
Datasheet Page 56 (p56_fig01)
P66 · p66_fig011748×1076px
STM32F765VIH6 (TFBGA-100) — 66/252 DS11532 Rev 7
66/252 DS11532 Rev 7
P105 · p105_fig011546×2099px
STM32F765VIH6 (TFBGA-100) — Figure 24. STM32F769xx/STM32F779xx power supply scheme
Figure 24. STM32F769xx/STM32F779xx power supply scheme
P105 · p105_fig01P105
STM32F765VIH6 (TFBGA-100) — Datasheet Page 105 (p105_fig01)
Datasheet Page 105 (p105_fig01)
P106 · p106_fig011551×2039px
STM32F765VIH6 (TFBGA-100) — Figure 25. STM32F765xx/STM32F767xx/STM32F777xx power supply scheme
Figure 25. STM32F765xx/STM32F767xx/STM32F777xx power supply scheme
Page 1 / 3 (32 extracted figures)

Technical Specifications & Part Details (STM32F765VIH6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F765VIH6 (TFBGA-100) is a 100-pin embedded microcontroller unit (mcu) featuring a 8.00 × 8.00 × 1.12 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 1.7 V to 3.6 V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.7 V to 3.6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
216 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
53 5V-tolerant (FT) pins detected
Package Envelope (D × E × A)D × E × A
8.00 × 8.00 × 1.12 mm (A1=0.25 mm)
Package family: BGA (TFBGA-100)
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, I2S, ADC, PWM, JTAG / SWD, IrDA, CAN, DAC, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol100 auto-grouped pins
OK
IPC-7351B Land Pattern100 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified
IPC-7351B

Family Variants & Same Datasheet Chips — STM32F765 / STM32F767 / STM32F769 (20)

Select package variant or sibling MPN sharing this datasheet

Mechanical Dimensions & Land Pattern (TFBGA-100)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
8.00 × 8.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.12mm · e=0.80mm
Pad Size (W × L)Level B
0.32 × 0.32 mm
Pins / Total PadsTopology
100P / 100Pad (BGA_GRID)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TFBGA-100
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — STM32F765VIH6 (TFBGA-100)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F765VIH6 (TFBGA-100)?

Manufactured by ST, the STM32F765VIH6 is housed in a TFBGA-100 package with 100 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 1.7 V to 3.6 V. Key pins include: A1 (PF1: Multiplexed I/O & Peripheral Pin PF1 (General)), A2 (PF2: Multiplexed I/O & Peripheral Pin PF2 (General)), A3 (PF3: Multiplexed I/O & Peripheral Pin PF3 (General)), A4 (PF4: Multiplexed I/O & Peripheral Pin PF4 (General)), A5 (PF5: Multiplexed I/O & Peripheral Pin PF5 (General)), A6 (PF12: Multiplexed I/O & Peripheral Pin PF12 (General)).

What are the IPC-7351B PCB Footprint dimensions for STM32F765VIH6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F765VIH6 (TFBGA-100) has a nominal body envelope of 8.00 × 8.00 mm, pitch e = 0.80 mm, and 100 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F765VIH6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F765VIH6 (ST, TFBGA-100) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (100 pins) & STM32F765 / STM32F767 / STM32F769 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
A1PF1Digital_IOSignal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General.
A2PF2Digital_IOSignal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General.
A3PF3Digital_IOSignal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General.
A4PF4Digital_IOSignal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General.
A5PF5Digital_IOSignal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General.
A6PF12Digital_IOSignal terminal PF12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF12. Supported peripheral buses: General.
A7PF13Digital_IOSignal terminal PF13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF13. Supported peripheral buses: General.
A8PF14Digital_IOSignal terminal PF14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF14. Supported peripheral buses: General.
A9PF15Digital_IOSignal terminal PF15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF15. Supported peripheral buses: General.
A10PG0Digital_IOSignal terminal PG0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG0. Supported peripheral buses: General.
B1PC15- OSC32_OUTDigital_IOSignal terminal PC15- OSC32_OUT (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC15- OSC32_OUT. Supported peripheral buses: RTC/CLK.
B2VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
B3PE3Digital_IOSignal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General.
B4PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C, CAN.
B5PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: UART, I2C.
B6PD5Digital_IOSignal terminal PD5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD5. Supported peripheral buses: UART.
B7PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
B8PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_MISORX. Supported peripheral buses: SPI.
B9PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: UART, SPI.
B10PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_CKUART4TX. Supported peripheral buses: UART, SPI, CAN.
C1PH0- OSC_INDigital_IOSignal terminal PH0- OSC_IN (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PH0- OSC_IN. Supported peripheral buses: RTC/CLK.
C2VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
C3PE4Digital_IOSignal terminal PE4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_NSS. Supported peripheral buses: SPI.
C4PE1Digital_IOSignal terminal PE1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PE1. Supported peripheral buses: UART.
C5PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI1_SDSPI3MOSI, SPI6MOSI. Supported peripheral buses: UART, SPI, CAN.
C6PD6Digital_IOSignal terminal PD6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD6. Supported peripheral buses: UART.
C7PD3Digital_IOSignal terminal PD3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD3. Supported peripheral buses: UART.
C8PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI3_SDUSART3. Supported peripheral buses: UART, SPI.
C9PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART, I2C.
C10PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_WSUART4RX. Supported peripheral buses: UART, SPI, PWM.
D1PD15Digital_IOSignal terminal PD15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD15. Supported peripheral buses: General.
D2PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: General.
D3PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: General.
D4PE7Digital_IOSignal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General.
D5PE8Digital_IOSignal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General.
D6PE9Digital_IOSignal terminal PE9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General.
D7PE10Digital_IOSignal terminal PE10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General.
D8PE11Digital_IOSignal terminal PE11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE11. Supported peripheral buses: General.
D9PE12Digital_IOSignal terminal PE12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE12. Supported peripheral buses: General.
D10PE13Digital_IOSignal terminal PE13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE13. Supported peripheral buses: General.
E1NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
E2PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: SPI, ADC.
E3PE6Digital_IOSignal terminal PE6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI4_MOSI. Supported peripheral buses: SPI.
E4VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E5VSSGND0V electrical ground return terminal (VSS) for internal core logic, I/O drivers, and analog sub-blocks.
E6BYPASS_REGDigital_IOSignal terminal BYPASS_REG (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: BYPASS_REG. Supported peripheral buses: General.
E7VCAP_2Digital_IOSignal terminal VCAP_2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_2. Supported peripheral buses: General.
E8PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: UART.
E9PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: I2C, RTC/CLK.
E10PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: PWM.
F1PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
F2PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: SPI2_M. Supported peripheral buses: SPI, I2C, ADC, RTC/CLK.
F3PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
F4VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F5VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F6VDDUSBPower_InPrimary positive power supply input (VDDUSB) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
F7PDR_ONDigital_IOSignal terminal PDR_ON (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PDR_ON. Supported peripheral buses: General.
F8VCAP_1Digital_IOSignal terminal VCAP_1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VCAP_1. Supported peripheral buses: General.
F9PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: UART.
F10PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: PWM.
G1VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
G2PA0- WKUPDigital_IOSignal terminal PA0- WKUP (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PA0- WKUP. Supported peripheral buses: UART, ADC.
G3PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: UART, SPI, ADC, DAC.
G4PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (5V-Tolerant FT) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: UART, ADC.
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