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CH547G (SOP-16) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH547G

WCHID: C1222433SOP-16 · 16 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH547G (SOP-16)102P1.4/SCS/AIN3P1.5/MOSI/PW4P1.6/MISO/RX5P1.7/SCK/TXD6P5.7/RST7P3.0/RXD8P3.1/TXD16V3315VDD14GND/VSS13P5.0/DM12P5.1/DP11P2.4/PWM1/T210P2.2/PWM3/IN9P3.4/T0Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.215.210.25.10-5.1-10.2-15.2mm
2. 2D FOOTPRINT
12345678910111213141516E=3.90mm · Pitch e=1.27mmD=9.90mm-6-5-4-3-2-1012345676543210-1-2-3-4-5-6-7mm
3. 3D CAD MODEL
Package Body: 3.90mm × 9.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (16/16)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
10I/OMultiplexed I/O & Peripheral Pin 0 (General)
2P1.4/SCS/AIN4I/OMultiplexed I/O & Peripheral Pin P1.4/SCS/AIN4 (ADC)
3P1.5/MOSI/PWM0_/AIN5I/OMultiplexed I/O & Peripheral Pin P1.5/MOSI/PWM0_/AIN5 (SPI, ADC, PWM)
4P1.6/MISO/RXD1_/AIN6I/OMultiplexed I/O & Peripheral Pin P1.6/MISO/RXD1_/AIN6 (UART, SPI, ADC)
5P1.7/SCK/TXD1_/AIN7I/OMultiplexed I/O & Peripheral Pin P1.7/SCK/TXD1_/AIN7 (UART, SPI, ADC)
6P5.7/RSTI/OMultiplexed I/O & Peripheral Pin P5.7/RST (General)
7P3.0/RXDI/OMultiplexed I/O & Peripheral Pin P3.0/RXD (UART)
8P3.1/TXDI/OMultiplexed I/O & Peripheral Pin P3.1/TXD (UART)
9P3.4/T0I/OMultiplexed I/O & Peripheral Pin P3.4/T0 (General)
10P2.2/PWM3/INT0_I/OMultiplexed I/O & Peripheral Pin P2.2/PWM3/INT0_ (PWM)
11P2.4/PWM1/T2_I/OMultiplexed I/O & Peripheral Pin P2.4/PWM1/T2_ (PWM)
12P5.1/DPI/OMultiplexed I/O & Peripheral Pin P5.1/DP (General)
13P5.0/DMI/OMultiplexed I/O & Peripheral Pin P5.0/DM (General)
14GND/VSSGNDGround Reference Pin (GND/VSS)
15VDDPowerPower Supply Input (VDD — 3.3V / 5.0V Standard Logic)
16V33PowerPower Supply Input (V33 — 3.3V / 5.0V Standard Logic)
PIN 1 0
I/O
Multiplexed I/O & Peripheral Pin 0 (General)
Design note: 输出系统主频的4 分频时钟信号 ，即Fsys/4
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH547G (WCH · SOP-16)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH547G (SOP-16) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH547G (SOP-16) - 2. Standard Pinout (Top View)
True package pinout (16 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH547G (SOP-16) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH547G (SOP-16) - 4. Package Dimensions (D×E×A)
SOP-16 · 3.90×9.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH547G (SOP-16) - 5. Recommended Land Pattern
IPC-7351B Footprint (16 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH547G (SOP-16) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH546 / CH547
P1 · p01_fig011717×914px
CH547G (SOP-16) — CH546 32KB+3KB 2 路 1 组 8 路 8 通道
CH546 32KB+3KB 2 路 1 组 8 路 8 通道
P27 · p27_fig011757×489px
CH547G (SOP-16) — 由Pn_MOD_OC[x]和Pn_DIR_PU[x]组合实现Pn 端口的相关配置，具体如下。
由Pn_MOD_OC[x]和Pn_DIR_PU[x]组合实现Pn 端口的相关配置，具体如下。
P28 · p28_fig011757×1897px
CH547G (SOP-16) — CH547 手册 28 | 0 | 1 | GND | Pn_DIR_PU[x] | Pn[x] | Delay 2 Clock | Pn[x] | OUT | bPn_MOD_OC[x] | 10K | 70K | VCC | VCC | // | AIN[x] | ADC_CHAN[x] VCC Pn[x] | IN | VCC | bPn_MOD_OC[x] | ADC_PIN[x/2] | P5 端口输入输出寄存器(P5)： | 位 名称 访问 描述 复位值 | 7
CH547 手册 28 | 0 | 1 | GND | Pn_DIR_PU[x] | Pn[x] | Delay 2 Clock | Pn[x] | OUT | bPn_MOD_OC[x] | 10K | 70K | VCC | VCC | // | AIN[x] | ADC_CHAN[x] VCC Pn[x] | IN | VCC | bPn_MOD_OC[x] | ADC_PIN[x/2] | P5 端口输入输出寄存器(P5)： | 位 名称 访问 描述 复位值 | 7
P28 · p28_fig01P28
CH547G (SOP-16) — Datasheet Page 28 (p28_fig01)
Datasheet Page 28 (p28_fig01)
P42 · p42_fig011757×798px
CH547G (SOP-16) — UART3 波特率由SBAUD3 设置产生，根据bU3SMOD 的选择分为两种情况： 当bU3SMOD=0 时，SBAUD3 = 256 - Fsys / 32 / 波特率； 当bU3SMOD=1 时，SBAUD3 = 256 - Fsys / 16 / 波特率。 UART3 中断状态寄存器(SIF3)： | 位 名称 访问 描述 复位值 | [7:2] 保留 RO 保留 000000b | 1 bU3TI RW 发送中断标志位，一个数据字节发送完后由硬件置位，需 要软件写1
UART3 波特率由SBAUD3 设置产生，根据bU3SMOD 的选择分为两种情况： 当bU3SMOD=0 时，SBAUD3 = 256 - Fsys / 32 / 波特率； 当bU3SMOD=1 时，SBAUD3 = 256 - Fsys / 16 / 波特率。 UART3 中断状态寄存器(SIF3)： | 位 名称 访问 描述 复位值 | [7:2] 保留 RO 保留 000000b | 1 bU3TI RW 发送中断标志位，一个数据字节发送完后由硬件置位，需 要软件写1
P45 · p45_fig011496×347px
CH547G (SOP-16) — 图14.3.1 SPI 模式0 时序图 模式3：bSn_MST_CLK = 1
图14.3.1 SPI 模式0 时序图 模式3：bSn_MST_CLK = 1
P45 · p45_fig021529×357px
CH547G (SOP-16) — 图14.3.1 SPI 模式0 时序图 模式3：bSn_MST_CLK = 1
图14.3.1 SPI 模式0 时序图 模式3：bSn_MST_CLK = 1
P60 · p60_fig01All Packages in PDF
CH547G (SOP-16) — 18.1 LQFP48-7*7 18.2 QFN28-4*4 70.15 #25 DOAQOHagegga ia COUN OT i. a — i= =a —_ im — —_ [ = pS 18 |8 | = a nls i — — |_| = = He ws =o aia Co #13 - = TInt aE ae Eee a spoon nag abs a oO. a.2 04 nh ne sos LQFP 1.5 TQFP |_|. 1.05
18.1 LQFP48-7*7 18.2 QFN28-4*4 70.15 #25 DOAQOHagegga ia COUN OT i. a — i= =a —_ im — —_ [ = pS 18 |8 | = a nls i — — |_| = = He ws =o aia Co #13 - = TInt aE ae Eee a spoon nag abs a oO. a.2 04 nh ne sos LQFP 1.5 TQFP |_|. 1.05

Technical Specifications & Part Details (CH547G)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH547G (SOP-16) is a 16-pin standard electronic & interconnect component featuring a 9.90 × 3.90 × 1.75 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART, SPI, ADC, PWM interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
40MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
9.90 × 3.90 × 1.75 mm (A1=0.15 mm)
Package family: SOP (SOP-16)
Pin Count & Lead PitchN / e
16 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART, SPI, ADC, PWM
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol16 auto-grouped pins
OK
IPC-7351B Land Pattern16 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOP-16)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
9.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.75mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
16P / 16Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOP-16
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH547G (SOP-16)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH547G (SOP-16)?

Manufactured by WCH, the CH547G is housed in a SOP-16 package with 16 pins and a 1.27 mm lead pitch. Key pins include: 1 (0: Multiplexed I/O & Peripheral Pin 0 (General)), 2 (P1.4/SCS/AIN4: Multiplexed I/O & Peripheral Pin P1.4/SCS/AIN4 (ADC)), 3 (P1.5/MOSI/PWM0_/AIN5: Multiplexed I/O & Peripheral Pin P1.5/MOSI/PWM0_/AIN5 (SPI, ADC, PWM)), 4 (P1.6/MISO/RXD1_/AIN6: Multiplexed I/O & Peripheral Pin P1.6/MISO/RXD1_/AIN6 (UART, SPI, ADC)), 5 (P1.7/SCK/TXD1_/AIN7: Multiplexed I/O & Peripheral Pin P1.7/SCK/TXD1_/AIN7 (UART, SPI, ADC)), 6 (P5.7/RST: Multiplexed I/O & Peripheral Pin P5.7/RST (General)).

What are the IPC-7351B PCB Footprint dimensions for CH547G?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH547G (SOP-16) has a nominal body envelope of 3.90 × 9.90 mm, pitch e = 1.27 mm, and 16 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH547G?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH547G (WCH, SOP-16) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (16 pins) & CH546 / CH547 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
10Digital_IOSignal terminal 0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: 0. Supported peripheral buses: General.
2P1.4/SCS/AIN4AnalogSignal terminal P1.4/SCS/AIN4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P1.4/SCS/AIN4. Supported peripheral buses: ADC.
3P1.5/MOSI/PWM0_/AIN5Digital_IOSignal terminal P1.5/MOSI/PWM0_/AIN5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: SPI, ADC, PWM.
4P1.6/MISO/RXD1_/AIN6Digital_IOSignal terminal P1.6/MISO/RXD1_/AIN6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI, ADC.
5P1.7/SCK/TXD1_/AIN7Digital_IOSignal terminal P1.7/SCK/TXD1_/AIN7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SPI. Supported peripheral buses: UART, SPI, ADC.
6P5.7/RSTDigital_IOSignal terminal P5.7/RST (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.7/RST. Supported peripheral buses: General.
7P3.0/RXDDigital_IOSignal terminal P3.0/RXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.0/RXD. Supported peripheral buses: UART.
8P3.1/TXDDigital_IOSignal terminal P3.1/TXD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.1/TXD. Supported peripheral buses: UART.
9P3.4/T0Digital_IOSignal terminal P3.4/T0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P3.4/T0. Supported peripheral buses: General.
10P2.2/PWM3/INT0_Digital_IOSignal terminal P2.2/PWM3/INT0_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.2/PWM3/INT0_. Supported peripheral buses: PWM.
11P2.4/PWM1/T2_Digital_IOSignal terminal P2.4/PWM1/T2_ (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P2.4/PWM1/T2_. Supported peripheral buses: PWM.
12P5.1/DPDigital_IOSignal terminal P5.1/DP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.1/DP. Supported peripheral buses: General.
13P5.0/DMDigital_IOSignal terminal P5.0/DM (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: P5.0/DM. Supported peripheral buses: General.
14GND/VSSGND0V electrical ground return terminal (GND/VSS) for internal core logic, I/O drivers, and analog sub-blocks.
15VDDPower_InPrimary positive power supply input (VDD) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
16V33Power_InPrimary positive power supply input (V33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
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