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SN65HVD230DR (SOIC-8) — Symbol, Footprint IPC-7351B & 3D STEP Model

SN65HVD230DR

TIID: C12084SOIC-8 · 8 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · SN65HVD230DR (SOIC-8)1D2GND3VCC4R8RS7CANH6CANL5VREFGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.810.25.10-5.1-10.2mm
2. 2D FOOTPRINT
12345678E=3.90mm · Pitch e=1.27mmD=4.90mm-5-4-3-2-101234543210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.90mm × 4.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (8/8)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DI/OMultiplexed I/O & Peripheral Pin D (General)
2GNDGNDGround Reference Pin (GND)
3VCCPowerPower Supply Input (VCC — 3 V to 6 V)
4RI/OMultiplexed I/O & Peripheral Pin R (General)
5VREFI/OMultiplexed I/O & Peripheral Pin VREF (General)
6CANLI/OMultiplexed I/O & Peripheral Pin CANL (CAN)
7CANHI/OMultiplexed I/O & Peripheral Pin CANH (CAN)
8RSI/OMultiplexed I/O & Peripheral Pin RS (General)
PIN 1 D
I/O
Multiplexed I/O & Peripheral Pin D (General)
Design note: Signal terminal D (I/O, 3 V to 6 V domain). Multiplexed alternate functions: D. Supported peripheral buses: General.
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: SN65HVD230DR (TI · SOIC-8)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
SN65HVD230DR (SOIC-8) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
SN65HVD230DR (SOIC-8) - 2. Standard Pinout (Top View)
True package pinout (8 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
SN65HVD230DR (SOIC-8) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
SN65HVD230DR (SOIC-8) - 4. Package Dimensions (D×E×A)
SOIC-8 · 3.90×4.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
SN65HVD230DR (SOIC-8) - 5. Recommended Land Pattern
IPC-7351B Footprint (8 Pads)Expand ›
6. Application SchematicSCHEMATIC
SN65HVD230DR (SOIC-8) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for SN65HVD230DR
P1 · p01_fig01883×1074px
SN65HVD230DR (SOIC-8) — NC – No internal connection
NC – No internal connection
P1 · p01_fig021906×723px
SN65HVD230DR (SOIC-8) — LOGIC DIAGRAM (POSITIVE LOGIC)
LOGIC DIAGRAM (POSITIVE LOGIC)
P1 · p01_fig03847×600px
SN65HVD230DR (SOIC-8) — LOGIC DIAGRAM (POSITIVE LOGIC)
LOGIC DIAGRAM (POSITIVE LOGIC)
P5 · p05_fig011339×1001px
SN65HVD230DR (SOIC-8) — CANH and CANL Inputs
CANH and CANL Inputs
P5 · p05_fig022835×1911px
SN65HVD230DR (SOIC-8) — D Input
D Input
P5 · p05_fig031380×641px
SN65HVD230DR (SOIC-8) — VCC
VCC
P5 · p05_fig041005×1141px
SN65HVD230DR (SOIC-8) — VCC | Output | 16 V | CANH and CANL Outputs | 20 V
VCC | Output | 16 V | CANH and CANL Outputs | 20 V
P5 · p05_fig051258×889px
SN65HVD230DR (SOIC-8) — R Output
R Output
P10 · p10_fig011991×1475px
SN65HVD230DR (SOIC-8) — Figure 4. Driver Test Circuit and Voltage Waveforms
Figure 4. Driver Test Circuit and Voltage Waveforms
P10 · p10_fig021877×581px
SN65HVD230DR (SOIC-8) — Figure 4. Driver Test Circuit and Voltage Waveforms
Figure 4. Driver Test Circuit and Voltage Waveforms
P10 · p10_fig01P10
SN65HVD230DR (SOIC-8) — Datasheet Page 10 (p10_fig01)
Datasheet Page 10 (p10_fig01)
P18 · p18_fig011963×1530px
SN65HVD230DR (SOIC-8) — Figure 27. The Layered ISO 11898 Standard Architecture
Figure 27. The Layered ISO 11898 Standard Architecture
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (SN65HVD230DR)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:SN65HVD230DR (SOIC-8) is a 8-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.75 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 3 V to 6 V supply operation across 40°C to 85°C with integrated CAN interfaces.
Operating Supply VoltageV_CC / V_DD
3 V to 6 V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
40°C to 85°C
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.90 × 1.75 mm (A1=0.00 mm)
Package family: SOIC (SOIC-8)
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
CAN
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol8 auto-grouped pins
OK
IPC-7351B Land Pattern8 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOIC-8)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.75mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
8P / 8Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOIC-8
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — SN65HVD230DR (SOIC-8)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of SN65HVD230DR (SOIC-8)?

Manufactured by TI, the SN65HVD230DR is housed in a SOIC-8 package with 8 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3 V to 6 V. Key pins include: 1 (D: Multiplexed I/O & Peripheral Pin D (General)), 2 (GND: Ground Reference Pin (GND)), 3 (VCC: Power Supply Input (VCC — 3 V to 6 V)), 4 (R: Multiplexed I/O & Peripheral Pin R (General)), 5 (VREF: Multiplexed I/O & Peripheral Pin VREF (General)), 6 (CANL: Multiplexed I/O & Peripheral Pin CANL (CAN)).

What are the IPC-7351B PCB Footprint dimensions for SN65HVD230DR?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), SN65HVD230DR (SOIC-8) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 8 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for SN65HVD230DR?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for SN65HVD230DR (TI, SOIC-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (8 pins) & SN65HVD230DR Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DDigital_IOSignal terminal D (I/O, 3 V to 6 V domain). Multiplexed alternate functions: D. Supported peripheral buses: General.
2GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
3VCCPower_InPrimary positive power supply input (VCC) operating in the 3 V to 6 V domain (Max rating: 6.0V).
4RDigital_IOSignal terminal R (I/O, 3 V to 6 V domain). Multiplexed alternate functions: R. Supported peripheral buses: General.
5VREFDigital_IOSignal terminal VREF (I/O, 3 V to 6 V domain). Multiplexed alternate functions: VREF. Supported peripheral buses: General.
6CANLDigital_IOSignal terminal CANL (I/O, 3 V to 6 V domain). Multiplexed alternate functions: CANL. Supported peripheral buses: CAN.
7CANHDigital_IOSignal terminal CANH (I/O, 3 V to 6 V domain). Multiplexed alternate functions: CANH. Supported peripheral buses: CAN.
8RSDigital_IOSignal terminal RS (I/O, 3 V to 6 V domain). Multiplexed alternate functions: RS. Supported peripheral buses: General.
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