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CH455H (SOP-18-300mil) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH455H

WCHID: C112928SOP-18-300mil · 18 Pins · Pitch 1.27mmIPC TOLERANCE VARIATION5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH455H (SOP-18-300mil)1DIG0 ～DIG32SCL3SDA4GND5DIG16DIG27DIG0 ～DIG38ISET9SEG0 ～SEG618INT#17SEG716SEG615SEG514SEG413SEG312SEG211VCC10SEG1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.217.812.77.62.5-2.5-7.6-12.7-17.8mm
2. 2D FOOTPRINT
123456789101112131415161718E=7.50mm · Pitch e=1.27mmD=11.55mm-8-6-4-20246897531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 7.50mm × 11.55mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (18/18)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1DIG0 ～DIG3I/OMultiplexed I/O & Peripheral Pin DIG0 ～DIG3 (General)
2SCLI/OMultiplexed I/O & Peripheral Pin SCL (I2C)
3SDAI/OMultiplexed I/O & Peripheral Pin SDA (I2C)
4GNDGNDGround Reference Pin (GND)
5DIG1I/OMultiplexed I/O & Peripheral Pin DIG1 (General)
6DIG2I/OMultiplexed I/O & Peripheral Pin DIG2 (General)
7DIG0 ～DIG3I/OMultiplexed I/O & Peripheral Pin DIG0 ～DIG3 (General)
8ISETI/OMultiplexed I/O & Peripheral Pin ISET (General)
9SEG0 ～SEG6I/OMultiplexed I/O & Peripheral Pin SEG0 ～SEG6 (General)
10SEG1I/OMultiplexed I/O & Peripheral Pin SEG1 (General)
11VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
12SEG2I/OMultiplexed I/O & Peripheral Pin SEG2 (General)
13SEG3I/OMultiplexed I/O & Peripheral Pin SEG3 (General)
14SEG4I/OMultiplexed I/O & Peripheral Pin SEG4 (General)
15SEG5I/OMultiplexed I/O & Peripheral Pin SEG5 (General)
16SEG6I/OMultiplexed I/O & Peripheral Pin SEG6 (General)
17SEG7I/OMultiplexed I/O & Peripheral Pin SEG7 (General)
18INT#I/OMultiplexed I/O & Peripheral Pin INT# (General)
PIN 1 DIG0 ～DIG3
I/O
Multiplexed I/O & Peripheral Pin DIG0 ～DIG3 (General)
Design note: 数码管的字驱动 低电平有效 ， ， 键盘扫描输出 高电平有效 ，
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 8 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH455H (WCH · SOP-18-300mil)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH455H (SOP-18-300mil) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH455H (SOP-18-300mil) - 2. Standard Pinout (Top View)
True package pinout (18 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH455H (SOP-18-300mil) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH455H (SOP-18-300mil) - 4. Package Dimensions (D×E×A)
SOP-18-300mil · 7.50×11.55mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH455H (SOP-18-300mil) - 5. Recommended Land Pattern
IPC-7351B Footprint (18 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH455H (SOP-18-300mil) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (8 figures · Page 1/1)
Showing 1–8 of 8 uncropped original figures for CH455
P1 · p01_fig011648×785px
CH455H (SOP-18-300mil) — CH455 是数码管显示驱动和键盘扫描控制芯片。CH455 内置时钟振荡电路，可以动态驱动4 位数 码管或者32 只LED；同时还可以进行28 键的键盘扫描；CH455 通过SCL 和SDA 组成的2 线串行接口 与单片机等交换数据。 | 2、特点 | DIG3～DIG0 | SEG6～0 | SEG7～SEG0 | INT# | SCL | SDA | CH455 芯片 | (虚线可选) | 单片机 | MCU 等 | 4 位 数码管 | 或 32 个 发光管 | 7×4
CH455 是数码管显示驱动和键盘扫描控制芯片。CH455 内置时钟振荡电路，可以动态驱动4 位数 码管或者32 只LED；同时还可以进行28 键的键盘扫描；CH455 通过SCL 和SDA 组成的2 线串行接口 与单片机等交换数据。 | 2、特点 | DIG3～DIG0 | SEG6～0 | SEG7～SEG0 | INT# | SCL | SDA | CH455 芯片 | (虚线可选) | 单片机 | MCU 等 | 4 位 数码管 | 或 32 个 发光管 | 7×4
P1 · p01_fig02884×391px
CH455H (SOP-18-300mil) — PDF Figure p01_fig02 (Page 1 — OTHER_DIAGRAM)
PDF Figure p01_fig02 (Page 1 — OTHER_DIAGRAM)
P1 · p01_fig01P1
CH455H (SOP-18-300mil) — Datasheet Page 1 (p01_fig01)
Datasheet Page 1 (p01_fig01)
P6 · p06_fig011490×451px
CH455H (SOP-18-300mil) — （注：本表计量单位以纳秒即10
（注：本表计量单位以纳秒即10
P8 · p08_fig011268×506px
CH455H (SOP-18-300mil) — 8.3. 简单应用：7 段×4＋7 键
8.3. 简单应用：7 段×4＋7 键
P8 · p08_fig021305×796px
CH455H (SOP-18-300mil) — 8.4. 简单应用：7 段×4＋4 键
8.4. 简单应用：7 段×4＋4 键
P9 · p09_fig011258×581px
CH455H (SOP-18-300mil) — 8.5. 抗干扰（重要）
8.5. 抗干扰（重要）
P9 · p09_fig021637×526px
CH455H (SOP-18-300mil) — 8.6. 单片机接口程序
8.6. 单片机接口程序

Technical Specifications & Part Details (CH455H)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH455H (SOP-18-300mil) is a 18-pin standard electronic & interconnect component featuring a 11.55 × 7.50 × 2.50 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
11.55 × 7.50 × 2.50 mm (A1=0.20 mm)
Package family: SOP (SOP-18-300mil)
Pin Count & Lead PitchN / e
18 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol18 auto-grouped pins
OK
IPC-7351B Land Pattern18 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOP-18-300mil)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
11.55 × 7.50 mm
Height (A) & Pitch (e)IPC-7351B
A=2.50mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.90 mm
Pins / Total PadsTopology
18P / 18Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOP-18-300mil
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH455H (SOP-18-300mil)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH455H (SOP-18-300mil)?

Manufactured by WCH, the CH455H is housed in a SOP-18-300mil package with 18 pins and a 1.27 mm lead pitch. Key pins include: 1 (DIG0 ～DIG3: Multiplexed I/O & Peripheral Pin DIG0 ～DIG3 (General)), 2 (SCL: Multiplexed I/O & Peripheral Pin SCL (I2C)), 3 (SDA: Multiplexed I/O & Peripheral Pin SDA (I2C)), 4 (GND: Ground Reference Pin (GND)), 5 (DIG1: Multiplexed I/O & Peripheral Pin DIG1 (General)), 6 (DIG2: Multiplexed I/O & Peripheral Pin DIG2 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH455H?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH455H (SOP-18-300mil) has a nominal body envelope of 7.50 × 11.55 mm, pitch e = 1.27 mm, and 18 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH455H?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH455H (WCH, SOP-18-300mil) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (18 pins) & CH455 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1DIG0 ～DIG3Digital_IOSignal terminal DIG0 ～DIG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG0 ～DIG3. Supported peripheral buses: General.
2SCLDigital_IOSignal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C.
3SDADigital_IOSignal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C.
4GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
5DIG1Digital_IOSignal terminal DIG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG1. Supported peripheral buses: General.
6DIG2Digital_IOSignal terminal DIG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG2. Supported peripheral buses: General.
7DIG0 ～DIG3Digital_IOSignal terminal DIG0 ～DIG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DIG0 ～DIG3. Supported peripheral buses: General.
8ISETDigital_IOSignal terminal ISET (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ISET. Supported peripheral buses: General.
9SEG0 ～SEG6Digital_IOSignal terminal SEG0 ～SEG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG0 ～SEG6. Supported peripheral buses: General.
10SEG1Digital_IOSignal terminal SEG1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG1. Supported peripheral buses: General.
11VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
12SEG2Digital_IOSignal terminal SEG2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG2. Supported peripheral buses: General.
13SEG3Digital_IOSignal terminal SEG3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG3. Supported peripheral buses: General.
14SEG4Digital_IOSignal terminal SEG4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG4. Supported peripheral buses: General.
15SEG5Digital_IOSignal terminal SEG5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG5. Supported peripheral buses: General.
16SEG6Digital_IOSignal terminal SEG6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG6. Supported peripheral buses: General.
17SEG7Digital_IOSignal terminal SEG7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SEG7. Supported peripheral buses: General.
18INT#Digital_IOSignal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General.
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