LQFP-100(14x14) · 100P
Synchronized Pinout (Symbol / 2D / 3D) (100/100)
Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D| Pin | Symbol | Type | Function (EN) |
|---|---|---|---|
| 1 | GPO | I/O | Multiplexed I/O & Peripheral Pin GPO (General) |
| 2 | GND | GND | Ground Reference Pin (GND) |
| 3 | GND | GND | Ground Reference Pin (GND) |
| 4 | RSVD | I/O | Multiplexed I/O & Peripheral Pin RSVD (General) |
| 5 | WAKE# | I/O | Multiplexed I/O & Peripheral Pin WAKE# (General) |
| 6 | RESET# | I | System Enable & Hardware Reset (RESET#) |
| 7 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 8 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 9 | GND | GND | Ground Reference Pin (GND) |
| 10 | VCC18 | Power | Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic) |
| 11 | PECKP | I/O | Multiplexed I/O & Peripheral Pin PECKP (General) |
| 12 | PECKN | I/O | Multiplexed I/O & Peripheral Pin PECKN (General) |
| 13 | VCC18A | Power | Power Supply Input (VCC18A — 3.3V / 5.0V Standard Logic) |
| 14 | GND | GND | Ground Reference Pin (GND) |
| 15 | GND | GND | Ground Reference Pin (GND) |
| 16 | RREF | I/O | Multiplexed I/O & Peripheral Pin RREF (General) |
| 17 | GND | GND | Ground Reference Pin (GND) |
| 18 | PERP | I/O | Multiplexed I/O & Peripheral Pin PERP (General) |
| 19 | PERN | I/O | Multiplexed I/O & Peripheral Pin PERN (General) |
| 20 | VCC18A | Power | Power Supply Input (VCC18A — 3.3V / 5.0V Standard Logic) |
| 21 | PETN | I/O | Multiplexed I/O & Peripheral Pin PETN (General) |
| 22 | PETP | I/O | Multiplexed I/O & Peripheral Pin PETP (General) |
| 23 | GND | GND | Ground Reference Pin (GND) |
| 24 | XO | I/O | XO (RTC/CLK) |
| 25 | XI | I/O | XI (RTC/CLK) |
| 26 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 27 | GND | GND | Ground Reference Pin (GND) |
| 28 | SCL | I/O | Multiplexed I/O & Peripheral Pin SCL (I2C) |
| 29 | SDA | I/O | Multiplexed I/O & Peripheral Pin SDA (I2C) |
| 30 | SDX | I/O | Multiplexed I/O & Peripheral Pin SDX (General) |
| 31 | SCS | I/O | Multiplexed I/O & Peripheral Pin SCS (General) |
| 32 | INT# | I/O | Multiplexed I/O & Peripheral Pin INT# (General) |
| 33 | INT2# | I/O | Multiplexed I/O & Peripheral Pin INT2# (General) |
| 34 | INT1# | I/O | Multiplexed I/O & Peripheral Pin INT1# (General) |
| 35 | INT0# | I/O | Multiplexed I/O & Peripheral Pin INT0# (General) |
| 36 | XCKI# | I/O | Multiplexed I/O & Peripheral Pin XCKI# (General) |
| 37 | GND | GND | Ground Reference Pin (GND) |
| 38 | RXD0 | I/O | Multiplexed I/O & Peripheral Pin RXD0 (UART) |
| 39 | DCD0 | I/O | Multiplexed I/O & Peripheral Pin DCD0 (General) |
| 40 | RI0 | I/O | Multiplexed I/O & Peripheral Pin RI0 (General) |
| 41 | DSR0 | I/O | Multiplexed I/O & Peripheral Pin DSR0 (UART) |
| 42 | CTS0 | I/O | Multiplexed I/O & Peripheral Pin CTS0 (UART) |
| 43 | RXD3 | I/O | Multiplexed I/O & Peripheral Pin RXD3 (UART) |
| 44 | DCD3 | I/O | Multiplexed I/O & Peripheral Pin DCD3 (General) |
| 45 | RI3 | I/O | Multiplexed I/O & Peripheral Pin RI3 (General) |
| 46 | DSR3 | I/O | Multiplexed I/O & Peripheral Pin DSR3 (UART) |
| 47 | CTS3 | I/O | Multiplexed I/O & Peripheral Pin CTS3 (UART) |
| 48 | VCC18 | Power | Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic) |
| 49 | GND | GND | Exposed Thermal & Ground Pad (GND) |
| 50 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 51 | RXD2 | I/O | Multiplexed I/O & Peripheral Pin RXD2 (UART) |
| 52 | DCD2 | I/O | Multiplexed I/O & Peripheral Pin DCD2 (General) |
| 53 | RI2 | I/O | Multiplexed I/O & Peripheral Pin RI2 (General) |
| 54 | DSR2 | I/O | Multiplexed I/O & Peripheral Pin DSR2 (UART) |
| 55 | CTS2 | I/O | Multiplexed I/O & Peripheral Pin CTS2 (UART) |
| 56 | RXD1 | I/O | Multiplexed I/O & Peripheral Pin RXD1 (UART) |
| 57 | DCD1 | I/O | Multiplexed I/O & Peripheral Pin DCD1 (General) |
| 58 | RI1 | I/O | Multiplexed I/O & Peripheral Pin RI1 (General) |
| 59 | DSR1 | I/O | Multiplexed I/O & Peripheral Pin DSR1 (UART) |
| 60 | CTS1 | I/O | Multiplexed I/O & Peripheral Pin CTS1 (UART) |
| 61 | GND | GND | Ground Reference Pin (GND) |
| 62 | D7 | I/O | Multiplexed I/O & Peripheral Pin D7 (General) |
| 63 | D6 | I/O | Multiplexed I/O & Peripheral Pin D6 (General) |
| 64 | D5 | I/O | Multiplexed I/O & Peripheral Pin D5 (General) |
| 65 | D4 | I/O | Multiplexed I/O & Peripheral Pin D4 (General) |
| 66 | D3 | I/O | Multiplexed I/O & Peripheral Pin D3 (General) |
| 67 | D2 | I/O | Multiplexed I/O & Peripheral Pin D2 (General) |
| 68 | D1 | I/O | Multiplexed I/O & Peripheral Pin D1 (General) |
| 69 | D0 | I/O | Multiplexed I/O & Peripheral Pin D0 (General) |
| 70 | VCC18 | Power | Power Supply Input (VCC18 — 3.3V / 5.0V Standard Logic) |
| 71 | GND | GND | Ground Reference Pin (GND) |
| 72 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 73 | TNOW1 | I/O | Multiplexed I/O & Peripheral Pin TNOW1 (General) |
| 74 | TNOW0 | I/O | Multiplexed I/O & Peripheral Pin TNOW0 (General) |
| 75 | CS1# | I/O | Multiplexed I/O & Peripheral Pin CS1# (General) |
| 76 | CS2# | I/O | Multiplexed I/O & Peripheral Pin CS2# (General) |
| 77 | GND | GND | Ground Reference Pin (GND) |
| 78 | TXD0 | I/O | Multiplexed I/O & Peripheral Pin TXD0 (UART) |
| 79 | RTS0 | I/O | Multiplexed I/O & Peripheral Pin RTS0 (UART) |
| 80 | DTR0 | I/O | Multiplexed I/O & Peripheral Pin DTR0 (UART) |
| 81 | TXD1 | I/O | Multiplexed I/O & Peripheral Pin TXD1 (UART) |
| 82 | RTS1 | I/O | Multiplexed I/O & Peripheral Pin RTS1 (UART) |
| 83 | DTR1 | I/O | Multiplexed I/O & Peripheral Pin DTR1 (UART) |
| 84 | TXD2 | I/O | Multiplexed I/O & Peripheral Pin TXD2 (UART) |
| 85 | RTS2 | I/O | Multiplexed I/O & Peripheral Pin RTS2 (UART) |
| 86 | GND | GND | Ground Reference Pin (GND) |
| 87 | VCC33 | Power | Power Supply Input (VCC33 — 3.3V / 5.0V Standard Logic) |
| 88 | DTR2 | I/O | Multiplexed I/O & Peripheral Pin DTR2 (UART) |
| 89 | TXD3 | I/O | Multiplexed I/O & Peripheral Pin TXD3 (UART) |
| 90 | RTS3 | I/O | Multiplexed I/O & Peripheral Pin RTS3 (UART) |
| 91 | DTR3 | I/O | Multiplexed I/O & Peripheral Pin DTR3 (UART) |
| 92 | XWR# | I/O | Multiplexed I/O & Peripheral Pin XWR# (General) |
| 93 | XRD# | I/O | Multiplexed I/O & Peripheral Pin XRD# (General) |
| 94 | ALE | I/O | Multiplexed I/O & Peripheral Pin ALE (General) |
| 95 | CS0# | I/O | Multiplexed I/O & Peripheral Pin CS0# (General) |
| 96 | GND | GND | Ground Reference Pin (GND) |
| 97 | MGND | GND | Ground Reference Pin (MGND) |
| 98 | MDSEL | I/O | Multiplexed I/O & Peripheral Pin MDSEL (General) |
| 99 | GND0 | GND | Ground Reference Pin (GND0) |
| 100 | CKSEL | I/O | Multiplexed I/O & Peripheral Pin CKSEL (General) |
PIN 1 GPO
I/OMultiplexed I/O & Peripheral Pin GPO (General)
Design note: 通用输出
IPC-7351B Solder Density & Span C/G/Z Tuner
Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)
Read the original datasheet PDF directly or click any drawing to view fullscreen1. Realistic 3D PackageREPRESENTATIVE
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
True package pinout (100 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
LQFP-100(14x14) · 14.00×14.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
IPC-7351B Footprint (100 Pads)Expand ›
6. Application SchematicSCHEMATIC
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH384
P1 · p01_fig011648×1149px
P1 · p01_fig021041×1041px
P1 · p01_fig01P1
P2 · p02_fig011732×2752px
P5 · p05_fig011957×1821px
Technical Specifications & Part Details (CH384L)
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)Detailed Overview:CH384L (LQFP-100(14x14)) is a 100-pin standard electronic & interconnect component featuring a 14.00 × 14.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated I2C, RTC/CLK, UART interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
14.00 × 14.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-100(14x14))
Pin Count & Lead PitchN / e
100 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
I2C, RTC/CLK, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.
5-Point Standards Verification
Automated compliance checks prior to exportIEEE-315 Symbol100 auto-grouped pins
IPC-7351B Land Pattern100 pads · Pitch 0.50mm
IPC-7525 60% Solder PasteReflow 1:1 Standard
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
Hardware Verification & Community Engineering Reviews
Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet5.00 PCB Verified
IPC-7351B
Select package variant or sibling MPN sharing this datasheetFamily Variants & Same Datasheet Chips — CH384 (2)
LQFP-100(14x14) · 100P
Mechanical Dimensions & Land Pattern (LQFP-100(14x14))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
14.00 × 14.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.50mm
Pad Size (W × L)Level B
0.30 × 1.25 mm
Pins / Total PadsTopology
100P / 100Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-100(14x14) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — CH384L (LQFP-100(14x14))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of CH384L (LQFP-100(14x14))?
Manufactured by WCH, the CH384L is housed in a LQFP-100(14x14) package with 100 pins and a 0.50 mm lead pitch. Key pins include: 1 (GPO: Multiplexed I/O & Peripheral Pin GPO (General)), 2 (GND: Ground Reference Pin (GND)), 3 (GND: Ground Reference Pin (GND)), 4 (RSVD: Multiplexed I/O & Peripheral Pin RSVD (General)), 5 (WAKE#: Multiplexed I/O & Peripheral Pin WAKE# (General)), 6 (RESET#: System Enable & Hardware Reset (RESET#)).
What are the IPC-7351B PCB Footprint dimensions for CH384L?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH384L (LQFP-100(14x14)) has a nominal body envelope of 14.00 × 14.00 mm, pitch e = 0.50 mm, and 100 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH384L?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH384L (WCH, LQFP-100(14x14)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (100 pins) & CH384 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | GPO | Digital_IO | Signal terminal GPO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: GPO. Supported peripheral buses: General. |
| 2 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 3 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 4 | RSVD | NC | Signal terminal RSVD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RSVD. Supported peripheral buses: General. |
| 5 | WAKE# | Digital_IO | Signal terminal WAKE# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WAKE#. Supported peripheral buses: General. |
| 6 | RESET# | Digital_IO | Active-low hardware reset terminal (RESET#): pulling this pin Low resets the processor core and peripherals. |
| 7 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 8 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 9 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 10 | VCC18 | Power_In | Primary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 11 | PECKP | Digital_IO | Signal terminal PECKP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKP. Supported peripheral buses: General. |
| 12 | PECKN | Digital_IO | Signal terminal PECKN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PECKN. Supported peripheral buses: General. |
| 13 | VCC18A | Power_In | Primary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 14 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 15 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 16 | RREF | Digital_IO | Signal terminal RREF (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RREF. Supported peripheral buses: General. |
| 17 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 18 | PERP | Digital_IO | Signal terminal PERP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERP. Supported peripheral buses: General. |
| 19 | PERN | Digital_IO | Signal terminal PERN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PERN. Supported peripheral buses: General. |
| 20 | VCC18A | Power_In | Primary positive power supply input (VCC18A) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 21 | PETN | Digital_IO | Signal terminal PETN (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETN. Supported peripheral buses: General. |
| 22 | PETP | Digital_IO | Signal terminal PETP (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: PETP. Supported peripheral buses: General. |
| 23 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 24 | XO | Digital_IO | 12 MHz crystal oscillator inverted output (XO); connect to crystal terminal and 22pF load capacitor to GND. |
| 25 | XI | Digital_IO | 12 MHz crystal oscillator input (XI); requires a 22pF load capacitor to GND (internally clocked on CH340C). |
| 26 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 27 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 28 | SCL | Digital_IO | Signal terminal SCL (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCL. Supported peripheral buses: I2C. |
| 29 | SDA | Digital_IO | Signal terminal SDA (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDA. Supported peripheral buses: I2C. |
| 30 | SDX | Digital_IO | Signal terminal SDX (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SDX. Supported peripheral buses: General. |
| 31 | SCS | Digital_IO | Signal terminal SCS (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: SCS. Supported peripheral buses: General. |
| 32 | INT# | Digital_IO | Signal terminal INT# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT#. Supported peripheral buses: General. |
| 33 | INT2# | Digital_IO | Signal terminal INT2# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT2#. Supported peripheral buses: General. |
| 34 | INT1# | Digital_IO | Signal terminal INT1# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT1#. Supported peripheral buses: General. |
| 35 | INT0# | Digital_IO | Signal terminal INT0# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT0#. Supported peripheral buses: General. |
| 36 | XCKI# | Digital_IO | Signal terminal XCKI# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XCKI#. Supported peripheral buses: General. |
| 37 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 38 | RXD0 | Digital_IO | Signal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART. |
| 39 | DCD0 | Digital_IO | Signal terminal DCD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD0. Supported peripheral buses: General. |
| 40 | RI0 | Digital_IO | Signal terminal RI0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI0. Supported peripheral buses: General. |
| 41 | DSR0 | Digital_IO | Signal terminal DSR0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR0. Supported peripheral buses: UART. |
| 42 | CTS0 | Digital_IO | Signal terminal CTS0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS0. Supported peripheral buses: UART. |
| 43 | RXD3 | Digital_IO | Signal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART. |
| 44 | DCD3 | Digital_IO | Signal terminal DCD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD3. Supported peripheral buses: General. |
| 45 | RI3 | Digital_IO | Signal terminal RI3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI3. Supported peripheral buses: General. |
| 46 | DSR3 | Digital_IO | Signal terminal DSR3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR3. Supported peripheral buses: UART. |
| 47 | CTS3 | Digital_IO | Signal terminal CTS3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS3. Supported peripheral buses: UART. |
| 48 | VCC18 | Power_In | Primary positive power supply input (VCC18) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 49 | GND | GND | Bottom exposed die attach pad (GND) providing primary thermal conduction path to the PCB and low-inductance 0V ground return. |
| 50 | VCC33 | Power_In | Primary positive power supply input (VCC33) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V). |
| 51 | RXD2 | Digital_IO | Signal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART. |
| 52 | DCD2 | Digital_IO | Signal terminal DCD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD2. Supported peripheral buses: General. |
| 53 | RI2 | Digital_IO | Signal terminal RI2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI2. Supported peripheral buses: General. |
| 54 | DSR2 | Digital_IO | Signal terminal DSR2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR2. Supported peripheral buses: UART. |
| 55 | CTS2 | Digital_IO | Signal terminal CTS2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS2. Supported peripheral buses: UART. |
| 56 | RXD1 | Digital_IO | Signal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART. |
| 57 | DCD1 | Digital_IO | Signal terminal DCD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DCD1. Supported peripheral buses: General. |
| 58 | RI1 | Digital_IO | Signal terminal RI1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RI1. Supported peripheral buses: General. |
| 59 | DSR1 | Digital_IO | Signal terminal DSR1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: DSR1. Supported peripheral buses: UART. |
| 60 | CTS1 | Digital_IO | Signal terminal CTS1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CTS1. Supported peripheral buses: UART. |
| 61 | GND | GND | 0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks. |
| 62 | D7 | Digital_IO | Signal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General. |
| 63 | D6 | Digital_IO | Signal terminal D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D6. Supported peripheral buses: General. |
| 64 | D5 | Digital_IO | Signal terminal D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5. Supported peripheral buses: General. |