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CH330N (SOP-8) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH330N

WCHID: C108996SOP-8 · 8 Pins · Pitch 1.27mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH330N (SOP-8)1UD+2UD-3GND4RTS#8V37RXD6TXD5VCCGrid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.210.25.10-5.1-10.2mm
2. 2D FOOTPRINT
12345678E=3.90mm · Pitch e=1.27mmD=4.90mm-5-4-3-2-101234543210-1-2-3-4mm
3. 3D CAD MODEL
Package Body: 3.90mm × 4.90mm · Pitch: 1.27mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (8/8)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1UD+I/OMultiplexed I/O & Peripheral Pin UD+ (USB)
2UD-I/OMultiplexed I/O & Peripheral Pin UD- (USB)
3GNDGNDGround Reference Pin (GND)
4RTS#I/ORTS# (UART)
5VCCPowerPower Supply Input (VCC — 3.3V to 5V)
6TXDI/OTXD (UART)
7RXDI/ORXD (UART)
8V3PowerRegulated Power Output (V3 — 3.3V to 5V)
PIN 1 UD+
I/O
Multiplexed I/O & Peripheral Pin UD+ (USB)
Design note: 直接连到USB总线的D+数据线
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 5 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH330N (WCH · SOP-8)
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH330N (SOP-8) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH330N (SOP-8) - 2. Standard Pinout (Top View)
True package pinout (8 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH330N (SOP-8) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH330N (SOP-8) - 4. Package Dimensions (D×E×A)
SOP-8 · 3.90×4.90mm · Pitch 1.27mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH330N (SOP-8) - 5. Recommended Land Pattern
IPC-7351B Footprint (8 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH330N (SOP-8) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (5 figures · Page 1/1)
Showing 1–5 of 5 uncropped original figures for CH330
P1 · p01_fig01EXACT PACKAGE
CH330N (SOP-8) — 封装形式 塑体宽度 引脚间距 封装说明 订货型号 SOP-8 3.9mm 150mil 1.27mm 50mil 标准的8 脚贴片 CH340N
封装形式 塑体宽度 引脚间距 封装说明 订货型号 SOP-8 3.9mm 150mil 1.27mm 50mil 标准的8 脚贴片 CH340N
P2 · p02_fig011706×1069px
CH330N (SOP-8) — 6.1. 绝对最大值（临界或者超过绝对最大值将可能导致芯片工作不正常甚至损坏）
6.1. 绝对最大值（临界或者超过绝对最大值将可能导致芯片工作不正常甚至损坏）
P2 · p02_fig021511×553px
CH330N (SOP-8) — V3 引脚的电容C2 容量为0.1μF，用于CH330 内部3.3V 电源节点退耦，C1 容量为0.1μF，用于 外部电源退耦。退耦电容C2 和C1 应该尽量靠近CH330 的相连引脚。 Ci C2 C26 c27 C29 vel W@.iu @.1u 4.47u US 4.47u 8. 47u ce vane MAK2Z32 Ri i 16 Pi] CH336 Sle. “Gs (2 L USB GND RTS# Stco+ y-[& oe _ . u- 1 up Slc2
V3 引脚的电容C2 容量为0.1μF，用于CH330 内部3.3V 电源节点退耦，C1 容量为0.1μF，用于 外部电源退耦。退耦电容C2 和C1 应该尽量靠近CH330 的相连引脚。 Ci C2 C26 c27 C29 vel W@.iu @.1u 4.47u US 4.47u 8. 47u ce vane MAK2Z32 Ri i 16 Pi] CH336 Sle. “Gs (2 L USB GND RTS# Stco+ y-[& oe _ . u- 1 up Slc2
P3 · p03_fig011366×528px
CH330N (SOP-8) — 二极管优先用小功率的Schottky 肖特基二极管，但普通二极管例如IN4148 通常也可以应用。 一般情况下，不建议CH330 与MCU 分开各自供电，仅在必要时使用。 c4 cS U2 CH338 UBUS B.iu8.1u P2 USB GMD von 1 UD- —_ D6 E: * ub+ [a | Ba528 " = t = j HJ) Poles THO d bP? BH. iu BAS?2a
二极管优先用小功率的Schottky 肖特基二极管，但普通二极管例如IN4148 通常也可以应用。 一般情况下，不建议CH330 与MCU 分开各自供电，仅在必要时使用。 c4 cS U2 CH338 UBUS B.iu8.1u P2 USB GMD von 1 UD- —_ D6 E: * ub+ [a | Ba528 " = t = j HJ) Poles THO d bP? BH. iu BAS?2a
P3 · p03_fig01P3
CH330N (SOP-8) — Datasheet Page 3 (p03_fig01)
Datasheet Page 3 (p03_fig01)

Technical Specifications & Part Details (CH330N)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH330N (SOP-8) is a 8-pin standard electronic & interconnect component featuring a 4.90 × 3.90 × 1.75 mm mechanical envelope (lead pitch e = 1.27 mm). Rated for 3.3V to 5V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.3V to 5V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
DC / Broadband Passive
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
4.90 × 3.90 × 1.75 mm (A1=0.15 mm)
Package family: SOP (SOP-8)
Pin Count & Lead PitchN / e
8 Pins | Pitch e = 1.27 mm (50.0 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol8 auto-grouped pins
OK
IPC-7351B Land Pattern8 pads · Pitch 1.27mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (SOP-8)

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
4.90 × 3.90 mm
Height (A) & Pitch (e)IPC-7351B
A=1.75mm · e=1.27mm
Pad Size (W × L)Level B
0.60 × 1.55 mm
Pins / Total PadsTopology
8P / 8Pad (DUAL_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
SOP-8
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH330N (SOP-8)

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH330N (SOP-8)?

Manufactured by WCH, the CH330N is housed in a SOP-8 package with 8 pins and a 1.27 mm lead pitch, supporting a VCC supply range of 3.3V to 5V. Key pins include: 1 (UD+: Multiplexed I/O & Peripheral Pin UD+ (USB)), 2 (UD-: Multiplexed I/O & Peripheral Pin UD- (USB)), 3 (GND: Ground Reference Pin (GND)), 4 (RTS#: RTS# (UART)), 5 (VCC: Power Supply Input (VCC — 3.3V to 5V)), 6 (TXD: TXD (UART)).

What are the IPC-7351B PCB Footprint dimensions for CH330N?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH330N (SOP-8) has a nominal body envelope of 3.90 × 4.90 mm, pitch e = 1.27 mm, and 8 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH330N?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH330N (WCH, SOP-8) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (8 pins) & CH330 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1UD+Digital_IOSignal terminal UD+ (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD+. Supported peripheral buses: USB.
2UD-Digital_IOSignal terminal UD- (I/O, 3.3V to 5V domain). Multiplexed alternate functions: UD-. Supported peripheral buses: USB.
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4RTS#Digital_IOMODEM hardware flow-control output signal (DTR# / RTS# active-low); commonly used for ESP32/Arduino auto-reset/bootloader entry.
5VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V to 5V domain (Max rating: 5.0V).
6TXDDigital_IOAsynchronous UART serial data output (TXD); cross-connect to the target MCU RXD pin.
7RXDDigital_IOAsynchronous UART serial data input (RXD) with built-in controllable pull-up and pull-down resistors.
8V3Power_OutRegulated power output rail (V3) operating in the 3.3V to 5V domain (Max rating: 5.0V).
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