ChipDocs.org
⌘K
2284 PARTSUpload PDF
CH438Q (LQFP-44(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

CH438Q

WCHID: C100039LQFP-44(10x10) · 44 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · CH438Q (LQFP-44(10x10))1WR#2VCC3GND4A6/ALE5A56A47ALE8A29A110A011RXD412TXD413TXD314GND15RXD316VCC17GND18XI19XO20RXD221TXD222TXD144RD#43CS#42AMOD41D040D139D238D337D436D535D634D733RST#32INT31RXD030TXD029RXD728TXD727RXD626TXD625RXD524TXD523RXD1Grid Pitch = 2.54mm (IEEE-315)-15.2-10.2-5.105.110.215.233.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344E=10.00mm · Pitch e=0.80mmD=10.00mm-10-8-6-4-202468101086420-2-4-6-8-10mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1WR#I/OMultiplexed I/O & Peripheral Pin WR# (General)
2VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
3GNDGNDGround Reference Pin (GND)
4A6/ALEI/OMultiplexed I/O & Peripheral Pin A6/ALE (General)
5A5I/OMultiplexed I/O & Peripheral Pin A5 (General)
6A4I/OMultiplexed I/O & Peripheral Pin A4 (General)
7ALEI/OMultiplexed I/O & Peripheral Pin ALE (General)
8A2I/OMultiplexed I/O & Peripheral Pin A2 (General)
9A1I/OMultiplexed I/O & Peripheral Pin A1 (General)
10A0I/OMultiplexed I/O & Peripheral Pin A0 (General)
11RXD4I/OMultiplexed I/O & Peripheral Pin RXD4 (UART)
12TXD4I/OMultiplexed I/O & Peripheral Pin TXD4 (UART)
13TXD3I/OMultiplexed I/O & Peripheral Pin TXD3 (UART)
14GNDGNDGround Reference Pin (GND)
15RXD3I/OMultiplexed I/O & Peripheral Pin RXD3 (UART)
16VCCPowerPower Supply Input (VCC — 3.3V / 5.0V Standard Logic)
17GNDGNDGround Reference Pin (GND)
18XII/OMultiplexed I/O & Peripheral Pin XI (RTC/CLK)
19XOI/OMultiplexed I/O & Peripheral Pin XO (RTC/CLK)
20RXD2I/OMultiplexed I/O & Peripheral Pin RXD2 (UART)
21TXD2I/OMultiplexed I/O & Peripheral Pin TXD2 (UART)
22TXD1I/OMultiplexed I/O & Peripheral Pin TXD1 (UART)
23RXD1I/OMultiplexed I/O & Peripheral Pin RXD1 (UART)
24TXD5I/OMultiplexed I/O & Peripheral Pin TXD5 (UART)
25RXD5I/OMultiplexed I/O & Peripheral Pin RXD5 (UART)
26TXD6I/OMultiplexed I/O & Peripheral Pin TXD6 (UART)
27RXD6I/OMultiplexed I/O & Peripheral Pin RXD6 (UART)
28TXD7I/OMultiplexed I/O & Peripheral Pin TXD7 (UART)
29RXD7I/OMultiplexed I/O & Peripheral Pin RXD7 (UART)
30TXD0I/OMultiplexed I/O & Peripheral Pin TXD0 (UART)
31RXD0I/OMultiplexed I/O & Peripheral Pin RXD0 (UART)
32INTI/OMultiplexed I/O & Peripheral Pin INT (General)
33RST#I/OMultiplexed I/O & Peripheral Pin RST# (General)
34D7I/OMultiplexed I/O & Peripheral Pin D7 (General)
35D6I/OMultiplexed I/O & Peripheral Pin D6 (General)
36D5I/OMultiplexed I/O & Peripheral Pin D5 (General)
37D4I/OMultiplexed I/O & Peripheral Pin D4 (General)
38D3I/OMultiplexed I/O & Peripheral Pin D3 (General)
39D2I/OMultiplexed I/O & Peripheral Pin D2 (General)
40D1I/OMultiplexed I/O & Peripheral Pin D1 (General)
41D0I/OMultiplexed I/O & Peripheral Pin D0 (General)
42AMODI/OMultiplexed I/O & Peripheral Pin AMOD (General)
43CS#I/OMultiplexed I/O & Peripheral Pin CS# (General)
44RD#I/OMultiplexed I/O & Peripheral Pin RD# (General)
PIN 1 WR#
I/O
Multiplexed I/O & Peripheral Pin WR# (General)
Design note: Writestrobeinputinparallelportmode activeatlow , level
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 4 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: CH438Q (WCH · LQFP-44(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
CH438Q (LQFP-44(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
CH438Q (LQFP-44(10x10)) - 2. Standard Pinout (Top View)
True package pinout (44 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
CH438Q (LQFP-44(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
CH438Q (LQFP-44(10x10)) - 4. Package Dimensions (D×E×A)
LQFP-44(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
CH438Q (LQFP-44(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (44 Pads)Expand ›
6. Application SchematicSCHEMATIC
CH438Q (LQFP-44(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (4 figures · Page 1/1)
Showing 1–4 of 4 uncropped original figures for CH438
P1 · p01_fig011772×1124px
CH438Q (LQFP-44(10x10)) — 2. Features | UART1 | UART7 | UART0 | UART2, 3, 4, 5 | UART6 | D7～D0 | ALE or A6～A0 | RD# | CS# | WR# | MCU | or ISA, etc. | Parallel | bus | CH438 | … … | TXD6/RTS6/DTR6 | RXD6/CTS6/DSR6/RI6/DCD6 | TXD1/RTS1/DTR1 | RXD1/CTS1/DSR1/RI1/DCD1
2. Features | UART1 | UART7 | UART0 | UART2, 3, 4, 5 | UART6 | D7～D0 | ALE or A6～A0 | RD# | CS# | WR# | MCU | or ISA, etc. | Parallel | bus | CH438 | … … | TXD6/RTS6/DTR6 | RXD6/CTS6/DSR6/RI6/DCD6 | TXD1/RTS1/DTR1 | RXD1/CTS1/DSR1/RI1/DCD1
P2 · p02_fig011458×1964px
CH438Q (LQFP-44(10x10)) — 3. Package
3. Package
P2 · p02_fig01P2
CH438Q (LQFP-44(10x10)) — Datasheet Page 2 (p02_fig01)
Datasheet Page 2 (p02_fig01)
P3 · p03_fig011719×1897px
CH438Q (LQFP-44(10x10)) — 2-6, 14, 15, 17-23, 41-43, 45, 58, 115-119, 121, 126, 127 NC. Idle | pin Connection disabled | 47 XI Input | Input terminal of the crystal oscillator, required to be | connected to an external crystal and oscillation | capacitor | 48 XO Out
2-6, 14, 15, 17-23, 41-43, 45, 58, 115-119, 121, 126, 127 NC. Idle | pin Connection disabled | 47 XI Input | Input terminal of the crystal oscillator, required to be | connected to an external crystal and oscillation | capacitor | 48 XO Out

Technical Specifications & Part Details (CH438Q)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:CH438Q (LQFP-44(10x10)) is a 44-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.40 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 1.8V ~ 5.5V (Theo Datasheet) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, RTC/CLK interfaces.
Operating Supply VoltageV_CC / V_DD
1.8V ~ 5.5V (Theo Datasheet)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
0.9216MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.40 mm (A1=0.10 mm)
Package family: LQFP (LQFP-44(10x10))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, RTC/CLK
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol44 auto-grouped pins
OK
IPC-7351B Land Pattern44 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-44(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.40mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.50 mm
Pins / Total PadsTopology
44P / 44Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
LQFP-44(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — CH438Q (LQFP-44(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of CH438Q (LQFP-44(10x10))?

Manufactured by WCH, the CH438Q is housed in a LQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch. Key pins include: 1 (WR#: Multiplexed I/O & Peripheral Pin WR# (General)), 2 (VCC: Power Supply Input (VCC — 3.3V / 5.0V Standard Logic)), 3 (GND: Ground Reference Pin (GND)), 4 (A6/ALE: Multiplexed I/O & Peripheral Pin A6/ALE (General)), 5 (A5: Multiplexed I/O & Peripheral Pin A5 (General)), 6 (A4: Multiplexed I/O & Peripheral Pin A4 (General)).

What are the IPC-7351B PCB Footprint dimensions for CH438Q?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), CH438Q (LQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for CH438Q?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for CH438Q (WCH, LQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & CH438 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1WR#Digital_IOSignal terminal WR# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: WR#. Supported peripheral buses: General.
2VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
3GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
4A6/ALEDigital_IOSignal terminal A6/ALE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A6/ALE. Supported peripheral buses: General.
5A5Digital_IOSignal terminal A5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A5. Supported peripheral buses: General.
6A4Digital_IOSignal terminal A4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A4. Supported peripheral buses: General.
7ALEDigital_IOSignal terminal ALE (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: ALE. Supported peripheral buses: General.
8A2Digital_IOSignal terminal A2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A2. Supported peripheral buses: General.
9A1Digital_IOSignal terminal A1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A1. Supported peripheral buses: General.
10A0Digital_IOSignal terminal A0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: A0. Supported peripheral buses: General.
11RXD4Digital_IOSignal terminal RXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD4. Supported peripheral buses: UART.
12TXD4Digital_IOSignal terminal TXD4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD4. Supported peripheral buses: UART.
13TXD3Digital_IOSignal terminal TXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD3. Supported peripheral buses: UART.
14GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
15RXD3Digital_IOSignal terminal RXD3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD3. Supported peripheral buses: UART.
16VCCPower_InPrimary positive power supply input (VCC) operating in the 3.3V / 5.0V Standard Logic domain (Max rating: 5.5V).
17GNDGND0V electrical ground return terminal (GND) for internal core logic, I/O drivers, and analog sub-blocks.
18XIDigital_IOSignal terminal XI (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XI. Supported peripheral buses: RTC/CLK.
19XODigital_IOSignal terminal XO (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: XO. Supported peripheral buses: RTC/CLK.
20RXD2Digital_IOSignal terminal RXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD2. Supported peripheral buses: UART.
21TXD2Digital_IOSignal terminal TXD2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD2. Supported peripheral buses: UART.
22TXD1Digital_IOSignal terminal TXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD1. Supported peripheral buses: UART.
23RXD1Digital_IOSignal terminal RXD1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD1. Supported peripheral buses: UART.
24TXD5Digital_IOSignal terminal TXD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD5. Supported peripheral buses: UART.
25RXD5Digital_IOSignal terminal RXD5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD5. Supported peripheral buses: UART.
26TXD6Digital_IOSignal terminal TXD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD6. Supported peripheral buses: UART.
27RXD6Digital_IOSignal terminal RXD6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD6. Supported peripheral buses: UART.
28TXD7Digital_IOSignal terminal TXD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD7. Supported peripheral buses: UART.
29RXD7Digital_IOSignal terminal RXD7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD7. Supported peripheral buses: UART.
30TXD0Digital_IOSignal terminal TXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: TXD0. Supported peripheral buses: UART.
31RXD0Digital_IOSignal terminal RXD0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RXD0. Supported peripheral buses: UART.
32INTDigital_IOSignal terminal INT (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: INT. Supported peripheral buses: General.
33RST#Digital_IOSignal terminal RST# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RST#. Supported peripheral buses: General.
34D7Digital_IOSignal terminal D7 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D7. Supported peripheral buses: General.
35D6Digital_IOSignal terminal D6 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D6. Supported peripheral buses: General.
36D5Digital_IOSignal terminal D5 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D5. Supported peripheral buses: General.
37D4Digital_IOSignal terminal D4 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D4. Supported peripheral buses: General.
38D3Digital_IOSignal terminal D3 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D3. Supported peripheral buses: General.
39D2Digital_IOSignal terminal D2 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D2. Supported peripheral buses: General.
40D1Digital_IOSignal terminal D1 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D1. Supported peripheral buses: General.
41D0Digital_IOSignal terminal D0 (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: D0. Supported peripheral buses: General.
42AMODDigital_IOSignal terminal AMOD (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: AMOD. Supported peripheral buses: General.
43CS#Digital_IOSignal terminal CS# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: CS#. Supported peripheral buses: General.
44RD#Digital_IOSignal terminal RD# (I/O, 3.3V / 5.0V Standard Logic domain). Multiplexed alternate functions: RD#. Supported peripheral buses: General.
ExplorePartsPackagesMFRsUpload