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PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

PIC24FJ48GA004-I/PT

MICROCHIPTQFP-44(10x10) · 44 Pins · Pitch 0.80mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · PIC24FJ48GA004-I/PT (TQFP-44(10x10))1I2C2ST3ST4ST5ST6ST7NC8ST9ST10ST11ST12IO713JTAGTestCloc14—15ST16—17—18ST19IO2020IO921ST22ST44I2C43ST42ST41ST40IO4039IO3938ST37ST36ST35JTAGTestData34Timer1Clock 33ANA32JTAGTestData31ST30ST29IO2928IO3327ST26ST25ST24I2C23I2CGrid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.833.027.922.917.812.77.62.5-2.5-7.6-12.7-17.8-22.9-27.9-33.0mm
2. 2D FOOTPRINT
1234567891011121314151617181920212223242526272829303132333435363738394041424344E=10.00mm · Pitch e=0.80mmD=10.00mm-10-8-6-4-202468101086420-2-4-6-8-10mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.80mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (44/44)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1I2CI/OMultiplexed I/O & Peripheral Pin I2C (I2C)
2STI/OMultiplexed I/O & Peripheral Pin ST (General)
3STI/OMultiplexed I/O & Peripheral Pin ST (General)
4STI/OMultiplexed I/O & Peripheral Pin ST (General)
5STI/OMultiplexed I/O & Peripheral Pin ST (General)
6STI/OMultiplexed I/O & Peripheral Pin ST (General)
7NCNCNo Connect (Leave Floating)
8STI/OMultiplexed I/O & Peripheral Pin ST (General)
9STI/OMultiplexed I/O & Peripheral Pin ST (General)
10STI/OMultiplexed I/O & Peripheral Pin ST (General)
11STI/OMultiplexed I/O & Peripheral Pin ST (General)
12IO7I/OGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13JTAGTestClockInput .I/OMultiplexed I/O & Peripheral Pin JTAGTestClockInput . (SWD/JTAG)
14—I/OMultiplexed I/O & Peripheral Pin — (RTC/CLK)
15STI/OMultiplexed I/O & Peripheral Pin ST (General)
16—I/OMultiplexed I/O & Peripheral Pin — (General)
17—I/OMultiplexed I/O & Peripheral Pin — (General)
18STI/OMultiplexed I/O & Peripheral Pin ST (General)
19IO20I/OGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9I/OGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21STI/OMultiplexed I/O & Peripheral Pin ST (General)
22STI/OMultiplexed I/O & Peripheral Pin ST (General)
23I2CI/OMultiplexed I/O & Peripheral Pin I2C (I2C)
24I2CI/OMultiplexed I/O & Peripheral Pin I2C (I2C)
25STI/OMultiplexed I/O & Peripheral Pin ST (General)
26STI/OMultiplexed I/O & Peripheral Pin ST (General)
27STI/OMultiplexed I/O & Peripheral Pin ST (General)
28IO33I/OGPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29IO29I/OGeneral Purpose Digital I/O Pin IO29
30STI/OMultiplexed I/O & Peripheral Pin ST (General)
31STI/OMultiplexed I/O & Peripheral Pin ST (General)
32JTAGTestDataOutput .I/OMultiplexed I/O & Peripheral Pin JTAGTestDataOutput . (SWD/JTAG)
33ANAI/OMultiplexed I/O & Peripheral Pin ANA (General)
34Timer1Clock .I/OMultiplexed I/O & Peripheral Pin Timer1Clock . (General)
35JTAGTestDataInput .I/OMultiplexed I/O & Peripheral Pin JTAGTestDataInput . (SWD/JTAG)
36STI/OMultiplexed I/O & Peripheral Pin ST (General)
37STI/OMultiplexed I/O & Peripheral Pin ST (General)
38STI/OMultiplexed I/O & Peripheral Pin ST (General)
39IO39I/OGeneral Purpose Digital I/O Pin IO39
40IO40I/OGeneral Purpose Digital I/O Pin IO40
41STI/OMultiplexed I/O & Peripheral Pin ST (General)
42STI/OMultiplexed I/O & Peripheral Pin ST (General)
43STI/OMultiplexed I/O & Peripheral Pin ST (General)
44I2CI/OMultiplexed I/O & Peripheral Pin I2C (I2C)
PIN 1 I2C
I/O
Multiplexed I/O & Peripheral Pin I2C (I2C)
Design note: SDA1
IPC-7351B Solder Density & Span C/G/Z Tuner

Extracted Drawings Gallery (6 Standard Drawings + 13 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
1. Realistic 3D PackageREPRESENTATIVE
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) - 2. Standard Pinout (Top View)
True package pinout (44 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) - 4. Package Dimensions (D×E×A)
TQFP-44(10x10) · 10.00×10.00mm · Pitch 0.80mmExpand ›
5. Recommended Land PatternLAND PATTERN
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (44 Pads)Expand ›
6. Application SchematicSCHEMATIC
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (13 figures · Page 1/2)
Showing 1–12 of 13 uncropped original figures for PIC24FJ48GA0
P1 · p01_fig01EXACT PACKAGE
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — 28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
P2 · p02_fig021233×532px
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — 10 11 | 2 3 | 6 | 1 | 18 19 20 21 | 22 | 12 13 14 15 8 7 16 17 | 23 24 25 26 27 28 | 9 | PIC24FJXXGA002 5 4 | VSS | PGED1/AN2/C2IN-/RP0/CN4/RB0 | OSCO/CLKO/CN29/PMA0/RA3 | OSCI/CLKI/CN30/RA2 | AN5/C1IN+/SCL2/RP3/CN7/RB3 | AN4/C1IN-/SDA2/RP2
10 11 | 2 3 | 6 | 1 | 18 19 20 21 | 22 | 12 13 14 15 8 7 16 17 | 23 24 25 26 27 28 | 9 | PIC24FJXXGA002 5 4 | VSS | PGED1/AN2/C2IN-/RP0/CN4/RB0 | OSCO/CLKO/CN29/PMA0/RA3 | OSCI/CLKI/CN30/RA2 | AN5/C1IN+/SCL2/RP3/CN7/RB3 | AN4/C1IN-/SDA2/RP2
P18 · p18_fig01867×940px
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS
FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS
P18 · p18_fig01P18
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — Datasheet Page 18 (p18_fig01)
Datasheet Page 18 (p18_fig01)
P20 · p20_fig01870×534px
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS
FIGURE 2-4: DC BIAS VOLTAGE vs. CAPACITANCE CHARACTERISTICS
P21 · p21_fig01867×1876px
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
FIGURE 2-5: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
P47 · p47_fig011405×786px
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS
P251 · p251_fig02466×357px
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — Example
Example
P251 · p251_fig041777×790px
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) —  2010-2013 Microchip Technology Inc. DS39881E-page 251 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custome
 2010-2013 Microchip Technology Inc. DS39881E-page 251 | Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for custome
P251 · p251_fig04P251
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — Datasheet Page 251 (p251_fig04)
Datasheet Page 251 (p251_fig04)
P2 · p02_fig01All Packages in PDF
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — 28-Pin QFN(1)
28-Pin QFN(1)
P251 · p251_fig01All Packages in PDF
PIC24FJ48GA004-I/PT (TQFP-44(10x10)) — 28-Lead SOIC (7.50 mm)
28-Lead SOIC (7.50 mm)
Page 1 / 2 (13 extracted figures)

Technical Specifications & Part Details (PIC24FJ48GA004-I/PT)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Standard Electronic & Interconnect Component
Detailed Overview:PIC24FJ48GA004-I/PT (TQFP-44(10x10)) is a 44-pin standard electronic & interconnect component featuring a 10.00 × 10.00 × 1.20 mm mechanical envelope (lead pitch e = 0.80 mm). Rated for 2.0V to 3.6V supply operation across -40°C ~ +85°C (Industrial Grade) with integrated UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG interfaces.
Operating Supply VoltageV_CC / V_DD
2.0V to 3.6V
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
32 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.20 mm (A1=0.10 mm)
Package family: TQFP (TQFP-44(10x10))
Pin Count & Lead PitchN / e
44 Pins | Pitch e = 0.80 mm (31.5 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
UART, SPI, I2C, ADC, PWM, JTAG / SWD, IrDA, RTC/CLK, SWD/JTAG
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Verify Pin-1 chamfer orientation on Top Silkscreen prior to SMT pick-and-place assembly.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol44 auto-grouped pins
OK
IPC-7351B Land Pattern44 pads · Pitch 0.80mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (TQFP-44(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.20mm · e=0.80mm
Pad Size (W × L)Level B
0.50 × 1.50 mm
Pins / Total PadsTopology
44P / 44Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
N/A
BOM
Per application circuit
TQFP-44(10x10)
Size power & signal trace widths for rated load current following IPC-2221 clearance rules.

Technical Frequently Asked Questions (FAQ) — PIC24FJ48GA004-I/PT (TQFP-44(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of PIC24FJ48GA004-I/PT (TQFP-44(10x10))?

Manufactured by MICROCHIP, the PIC24FJ48GA004-I/PT is housed in a TQFP-44(10x10) package with 44 pins and a 0.80 mm lead pitch, supporting a VCC supply range of 2.0V to 3.6V. Key pins include: 1 (I2C: Multiplexed I/O & Peripheral Pin I2C (I2C)), 2 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 3 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 4 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 5 (ST: Multiplexed I/O & Peripheral Pin ST (General)), 6 (ST: Multiplexed I/O & Peripheral Pin ST (General)).

What are the IPC-7351B PCB Footprint dimensions for PIC24FJ48GA004-I/PT?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), PIC24FJ48GA004-I/PT (TQFP-44(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.80 mm, and 44 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for PIC24FJ48GA004-I/PT?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for PIC24FJ48GA004-I/PT (MICROCHIP, TQFP-44(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (44 pins) & PIC24FJ48GA0 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1I2CDigital_IOSignal terminal I2C (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: I2C. Supported peripheral buses: I2C.
2STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
3STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
4STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
5STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
6STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
7NCNo_ConnectNo Connect (Leave Floating)
8STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
9STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
10STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
11STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
12IO7Digital_IOGPIO7 / RTC_GPIO7 / TOUCH7 / ADC1_CH6
13JTAGTestClockInput .Digital_IOSignal terminal JTAGTestClockInput . (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: JTAGTestClockInput .. Supported peripheral buses: SWD/JTAG.
14—Digital_IOSignal terminal — (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: RTC/CLK.
15STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
16—Digital_IOSignal terminal — (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
17—Digital_IOSignal terminal — (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: —. Supported peripheral buses: General.
18STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
19IO20Digital_IOGPIO20 / RTC_GPIO20 / USB_D+ / U1CTS / ADC2_CH9
20IO9Digital_IOGPIO9 / RTC_GPIO9 / TOUCH9 / ADC1_CH8 / FSPIHD
21STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
22STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
23I2CDigital_IOSignal terminal I2C (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: I2C. Supported peripheral buses: I2C.
24I2CDigital_IOSignal terminal I2C (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: I2C. Supported peripheral buses: I2C.
25STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
26STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
27STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
28IO33Digital_IOGPIO33 / FSPIHD / SUBSPIHD / SPIIO4
29IO29Digital_IOGeneral Purpose Digital I/O Pin IO29
30STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
31STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
32JTAGTestDataOutput .Digital_IOSignal terminal JTAGTestDataOutput . (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: JTAGTestDataOutput .. Supported peripheral buses: SWD/JTAG.
33ANADigital_IOSignal terminal ANA (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ANA. Supported peripheral buses: General.
34Timer1Clock .Digital_IOSignal terminal Timer1Clock . (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: Timer1Clock .. Supported peripheral buses: General.
35JTAGTestDataInput .AnalogSignal terminal JTAGTestDataInput . (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: JTAGTestDataInput .. Supported peripheral buses: SWD/JTAG.
36STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
37STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
38STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
39IO39Digital_IOGeneral Purpose Digital I/O Pin IO39
40IO40Digital_IOGeneral Purpose Digital I/O Pin IO40
41STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
42STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
43STDigital_IOSignal terminal ST (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: ST. Supported peripheral buses: General.
44I2CDigital_IOSignal terminal I2C (I/O, 2.0V to 3.6V domain). Multiplexed alternate functions: I2C. Supported peripheral buses: I2C.
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