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STM32F103RCT6 (LQFP-64(10x10)) — Symbol, Footprint IPC-7351B & 3D STEP Model

STM32F103RCT6

STID: C8323LQFP-64(10x10) · 64 Pins · Pitch 0.50mmIPC-7351B Verified5.0 (0)
SYNCHRONIZED 4D CROSS-PROBE MODETouch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
1. SYMBOL
U1 · STM32F103RCT6 (LQFP-64(10x10))1VBAT2PC13TAMPER -3PC14 - OSC324PC15 - OSC325PD06PD17NRST8PC09PC110PC211PC312VSSA13VDDA14PA0WKUP -15PA116PA217PA318VSS_419VDD_420PA421PA522PA623PA724PC425PC526PB027PB128PB229PB1030PB1131VSS_132VDD_164VDD_363VSS_362PB961PB860BOOT059PB758PB657PB556PB455PB354PD253PC1252PC1151PC1050PA1549PA1448VDD_247VSS_246PA1345PA1244PA1143PA1042PA941PA840PC939PC838PC737PC636PB1535PB1434PB1333PB12Grid Pitch = 2.54mm (IEEE-315)-17.8-12.7-7.6-2.52.57.612.717.845.740.635.630.525.420.315.210.25.10-5.1-10.2-15.2-20.3-25.4-30.5-35.6-40.6-45.7mm
2. 2D FOOTPRINT
12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364E=10.00mm · Pitch e=0.50mmD=10.00mm-9-7-5-3-11357997531-1-3-5-7-9mm
3. 3D CAD MODEL
Package Body: 10.00mm × 10.00mm · Pitch: 0.50mm · Ruler Step: 1.00mmSynced <100ms

Synchronized Pinout (Symbol / 2D / 3D) (64/64)

Touch or hover any pin to highlight concurrently across Symbol, Footprint and 3D
PinSymbolTypeFunction (EN)
1VBATPowerPower Supply Input (VBAT — 3.3V VDD (Max 4.0V))
2PC13TAMPER - - RTCI/OMultiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)
3PC14 - OSC32 IN(5)_I/OMultiplexed I/O & Peripheral Pin PC14 - OSC32 IN(5)_ (RTC/CLK)
4PC15 - OSC32 OUT(5)_I/OMultiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(5)_ (RTC/CLK)
5PD0I/OMultiplexed I/O & Peripheral Pin PD0 (RTC/CLK)
6PD1I/OMultiplexed I/O & Peripheral Pin PD1 (RTC/CLK)
7NRSTISystem Enable & Hardware Reset (NRST)
8PC0I/OMultiplexed I/O & Peripheral Pin PC0 (ADC)
9PC1I/OMultiplexed I/O & Peripheral Pin PC1 (ADC)
10PC2I/OMultiplexed I/O & Peripheral Pin PC2 (ADC)
11PC3I/OMultiplexed I/O & Peripheral Pin PC3 (ADC)
12VSSAGNDGround Reference Pin (VSSA)
13VDDAPowerPower Supply Input (VDDA — 3.3V VDD (Max 4.0V))
14PA0WKUP -I/OMultiplexed I/O & Peripheral Pin PA0WKUP - (UART, ADC, PWM)
15PA1I/OMultiplexed I/O & Peripheral Pin PA1 (UART, ADC)
16PA2I/OMultiplexed I/O & Peripheral Pin PA2 (UART, ADC, PWM)
17PA3I/OMultiplexed I/O & Peripheral Pin PA3 (UART, PWM)
18VSS_4GNDGround Reference Pin (VSS_4)
19VDD_4PowerPower Supply Input (VDD_4 — 3.3V VDD (Max 4.0V))
20PA4I/OMultiplexed I/O & Peripheral Pin PA4 (SPI, ADC, DAC)
21PA5I/OMultiplexed I/O & Peripheral Pin PA5 (SPI, DAC)
22PA6I/OMultiplexed I/O & Peripheral Pin PA6 (SPI, ADC)
23PA7I/OMultiplexed I/O & Peripheral Pin PA7 (SPI, ADC)
24PC4I/OMultiplexed I/O & Peripheral Pin PC4 (ADC)
25PC5I/OMultiplexed I/O & Peripheral Pin PC5 (ADC)
26PB0I/OMultiplexed I/O & Peripheral Pin PB0 (ADC, PWM)
27PB1I/OMultiplexed I/O & Peripheral Pin PB1 (ADC, PWM)
28PB2I/OMultiplexed I/O & Peripheral Pin PB2 (General)
29PB10I/OMultiplexed I/O & Peripheral Pin PB10 (UART, I2C)
30PB11I/OMultiplexed I/O & Peripheral Pin PB11 (UART, I2C)
31VSS_1GNDGround Reference Pin (VSS_1)
32VDD_1PowerPower Supply Input (VDD_1 — 3.3V VDD (Max 4.0V))
33PB12I/OMultiplexed I/O & Peripheral Pin PB12 (UART, SPI, I2C)
34PB13I/OMultiplexed I/O & Peripheral Pin PB13 (UART, SPI, PWM)
35PB14I/OMultiplexed I/O & Peripheral Pin PB14 (UART, SPI, PWM)
36PB15I/OMultiplexed I/O & Peripheral Pin PB15 (SPI)
37PC6I/OMultiplexed I/O & Peripheral Pin PC6 (General)
38PC7I/OMultiplexed I/O & Peripheral Pin PC7 (General)
39PC8I/OMultiplexed I/O & Peripheral Pin PC8 (General)
40PC9I/OMultiplexed I/O & Peripheral Pin PC9 (General)
41PA8I/OMultiplexed I/O & Peripheral Pin PA8 (UART, RTC/CLK)
42PA9I/OMultiplexed I/O & Peripheral Pin PA9 (UART)
43PA10I/OMultiplexed I/O & Peripheral Pin PA10 (UART)
44PA11I/OMultiplexed I/O & Peripheral Pin PA11 (USB, UART, CAN)
45PA12I/OMultiplexed I/O & Peripheral Pin PA12 (USB, UART, CAN)
46PA13I/OMultiplexed I/O & Peripheral Pin PA13 (SWD/JTAG)
47VSS_2GNDGround Reference Pin (VSS_2)
48VDD_2PowerPower Supply Input (VDD_2 — 3.3V VDD (Max 4.0V))
49PA14I/OMultiplexed I/O & Peripheral Pin PA14 (SWD/JTAG)
50PA15I/OMultiplexed I/O & Peripheral Pin PA15 (SPI, SWD/JTAG)
51PC10I/OMultiplexed I/O & Peripheral Pin PC10 (UART)
52PC11I/OMultiplexed I/O & Peripheral Pin PC11 (UART)
53PC12I/OMultiplexed I/O & Peripheral Pin PC12 (UART)
54PD2I/OMultiplexed I/O & Peripheral Pin PD2 (UART)
55PB3I/OMultiplexed I/O & Peripheral Pin PB3 (SPI, SWD/JTAG)
56PB4I/OMultiplexed I/O & Peripheral Pin PB4 (SPI, SWD/JTAG)
57PB5I/OMultiplexed I/O & Peripheral Pin PB5 (SPI, I2C)
58PB6I/OMultiplexed I/O & Peripheral Pin PB6 (I2C)
59PB7I/OMultiplexed I/O & Peripheral Pin PB7 (I2C)
60BOOT0IInput-Only Pin BOOT0 (General)
61PB8I/OMultiplexed I/O & Peripheral Pin PB8 (General)
62PB9I/OMultiplexed I/O & Peripheral Pin PB9 (General)
63VSS_3GNDGround Reference Pin (VSS_3)
64VDD_3PowerPower Supply Input (VDD_3 — 3.3V VDD (Max 4.0V))
PIN 1 VBAT
Power
Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))
Design note: VBAT
IPC-7351B Solder Density & Span C/G/Z Tuner

Live Embedded Datasheet PDF & Technical Drawing Gallery (6 Standard Drawings + 14 Extracted Figures)

Read the original datasheet PDF directly or click any drawing to view fullscreen
Open PDF in New Window ↗Read Datasheet PDF (.pdf)
PDF VIEWEROfficial Datasheet Document: STM32F103RCT6 (ST · LQFP-64(10x10))
Scroll, search text (Ctrl+F), or expand directly inside the embedded PDF reader below
1. Realistic 3D PackageREPRESENTATIVE
STM32F103RCT6 (LQFP-64(10x10)) - 1. Realistic 3D Package
Detailed solid 3D bodyExpand ›
2. Standard Pinout (Top View)CLEANROOM PINOUT
STM32F103RCT6 (LQFP-64(10x10)) - 2. Standard Pinout (Top View)
True package pinout (64 pins)Expand ›
3. Original Datasheet PinoutPDF PINOUT
STM32F103RCT6 (LQFP-64(10x10)) - 3. Original Datasheet Pinout
Uncropped datasheet pin diagramExpand ›
4. Package Dimensions (D×E×A)PACKAGE DIMENSIONS
STM32F103RCT6 (LQFP-64(10x10)) - 4. Package Dimensions (D×E×A)
LQFP-64(10x10) · 10.00×10.00mm · Pitch 0.50mmExpand ›
5. Recommended Land PatternLAND PATTERN
STM32F103RCT6 (LQFP-64(10x10)) - 5. Recommended Land Pattern
IPC-7351B Footprint (64 Pads)Expand ›
6. Application SchematicSCHEMATIC
STM32F103RCT6 (LQFP-64(10x10)) - 6. Application Schematic
Typical Application SchematicExpand ›
Original Datasheet Pinouts & Technical Drawings (14 figures · Page 1/2)
Showing 1–12 of 14 uncropped original figures for STM32F103
P29 · p29_fig01EXACT PACKAGE
STM32F103RCT6 (LQFP-64(10x10)) — Figure 7. STM32F103xC/D/E performance line LQFP64 pinout
Figure 7. STM32F103xC/D/E performance line LQFP64 pinout
P129 · p129_fig01EXACT PACKAGE
STM32F103RCT6 (LQFP-64(10x10)) — Figure 76. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline 6($7,1*3/$1( &
Figure 76. LQFP64 - 10 x 10 mm 64 pin low-profile quad flat package outline 6($7,1*3/$1( &
P130 · p130_fig01EXACT PACKAGE
STM32F103RCT6 (LQFP-64(10x10)) — Figure 77. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint
Figure 77. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint
P142 · p142_fig01EXACT PACKAGE
STM32F103RCT6 (LQFP-64(10x10)) — Revision history STM32F103xC, STM32F103xD, STM32F103xE
Revision history STM32F103xC, STM32F103xD, STM32F103xE
P1 · p01_fig01881×446px
STM32F103RCT6 (LQFP-64(10x10)) — High-density performance line Arm®-based 32-bit MCU with 256 to 512KB
High-density performance line Arm®-based 32-bit MCU with 256 to 512KB
P29 · p29_fig01P29
STM32F103RCT6 (LQFP-64(10x10)) — Datasheet Page 29 (p29_fig01)
Datasheet Page 29 (p29_fig01)
P42 · p42_fig011546×1184px
STM32F103RCT6 (LQFP-64(10x10)) — Figure 12. Power supply scheme sd
Figure 12. Power supply scheme sd
P42 · p42_fig021540×740px
STM32F103RCT6 (LQFP-64(10x10)) — Figure 13. Current consumption measurement scheme
Figure 13. Current consumption measurement scheme
P42 · p42_fig01P42
STM32F103RCT6 (LQFP-64(10x10)) — Datasheet Page 42 (p42_fig01)
Datasheet Page 42 (p42_fig01)
P60 · p60_fig011546×483px
STM32F103RCT6 (LQFP-64(10x10)) — Figure 22. Typical application with an 8 MHz crystal
Figure 22. Typical application with an 8 MHz crystal
P62 · p62_fig011751×666px
STM32F103RCT6 (LQFP-64(10x10)) — Figure 23. Typical application with a 32.768 kHz crystal
Figure 23. Typical application with a 32.768 kHz crystal
P129 · p129_fig01P129
STM32F103RCT6 (LQFP-64(10x10)) — Datasheet Page 129 (p129_fig01)
Datasheet Page 129 (p129_fig01)
Page 1 / 2 (14 extracted figures)

Technical Specifications & Part Details (STM32F103RCT6)

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet (EN)
Embedded Microcontroller Unit (MCU)
Detailed Overview:STM32F103RCT6 (LQFP-64(10x10)) is a 64-pin embedded microcontroller unit (mcu) featuring a 10.00 × 10.00 × 1.60 mm mechanical envelope (lead pitch e = 0.50 mm). Rated for 3.0V ~ 3.6V (Typ 3.3V) supply operation across -40°C ~ +85°C (Industrial Grade) with integrated USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART interfaces.
Operating Supply VoltageV_CC / V_DD
3.0V ~ 3.6V (Typ 3.3V)
Place 100nF + 10µF X7R decoupling capacitors < 2mm from supply pins
Ambient Operating TemperatureT_A
-40°C ~ +85°C (Industrial Grade)
Industrial temperature grade; T_J(max) = +125°C
Clock / RF Operating Frequencyf_CLK / f_RF
72 MHz
Extracted from authoritative PDF specification tables
Current & Power RatingI_OUT / I_CC
I_GPIO(max) = ±20 mA / pin | I_VDD(total) ≤ 150 mA
Observe per-pin absolute maximum current limits
Package Envelope (D × E × A)D × E × A
10.00 × 10.00 × 1.60 mm (A1=0.10 mm)
Package family: LQFP (LQFP-64(10x10))
Pin Count & Lead PitchN / e
64 Pins | Pitch e = 0.50 mm (19.7 mil)
Normalized to Center-to-Center Span C per IPC-7351B
Integrated Peripheral InterfacesBuses
USB, SPI, I2C, I2S, ADC, DAC, PWM, SDIO, JTAG / SWD, IrDA, CAN, RTC/CLK, SWD/JTAG, UART
Cross-linked with 4D Pinout & Schematic Symbol
Reflow & Moisture SensitivityIPC / MSL
IPC-7351B Level B | J-STD-020 (Peak 260°C) | MSL-3
60% windowed solder paste stencil on thermal EPAD
Engineering Safety Alert: Boot Strapping Pin Alert (PB2, BOOT0): Do not force conflicting external pull-ups/pull-downs during POR reset.
Engineering Safety Alert: Connect exposed thermal pad (if present) to internal ground plane via 0.3mm stitched thermal vias.

5-Point Standards Verification

Automated compliance checks prior to export
5/5 PASS
IEEE-315 Symbol64 auto-grouped pins
OK
IPC-7351B Land Pattern64 pads · Pitch 0.50mm
OK
IPC-7525 60% Solder PasteReflow 1:1 Standard
OK
DFM Rules JLCPCB / PCBWayMin pad clearance: 0.25mm
OK
3D STEP AP214 & GLBAligned coordinate origin (0,0,0)
OK

Hardware Verification & Community Engineering Reviews

Summary of electrical parameters, mechanical dimensions, voltage range and peripheral interfaces from Datasheet
5.00 PCB Verified

Mechanical Dimensions & Land Pattern (LQFP-64(10x10))

Extracted from Datasheet & IPC-7351B Normalized
mm
Package Body (D × E)Nominal
10.00 × 10.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.27 × 1.30 mm
Pins / Total PadsTopology
64P / 64Pad (QUAD_ROW)

Recommended Companion BOM & Drop-In Equivalents

Passive external components per reference schematic and 1:1 pin-compatible alternatives
DFM READY
Designator / Replacement MPNValue / PackageFunction & PCB Layout Rule
C1, C2, C3
BOM
3× 100nF (0.1µF) 50V X7R
0402 / 0603
Digital supply decoupling caps for VDD_1..3 (Pins 24, 36, 48) — place < 1.5mm from each VDD pin.
C4
BOM
4.7µF ~ 10µF 10V X5R
0603 / 0805
Bulk decoupling capacitor for main VDD rail — place near 3.3V power entry to the MCU.
C5, C6 + FB1
BOM
100nF + 1µF + Ferrite 600Ω@100MHz
0402 / 0603
Analog rail filter for VDDA/VSSA (Pins 8, 9) 12-bit ADC — isolate digital switching noise.
Y1 + C7, C8
BOM
8MHz Crystal (CL=12pF) + 2× 18pF NP0
SMD-3225 + 0402
Main HSE oscillator crystal (Pin 5 PD0, Pin 6 PD1) — route matched traces < 4mm with GND guard ring.
STM32F103CBT6
STMicroelectronics
100% Drop-in100% Drop-in (128KB Flash Upgrade) — identical LQFP-48 pinout with doubled Flash capacity.
GD32F103C8T6
GigaDevice
Pin-to-Pin LQFP-48 (108MHz)Pin-to-Pin LQFP-48 (108MHz) — higher core clock; verify Flash wait-states & USB timing.
APM32F103C8T6
Geehy
Pin-to-Pin LQFP-48 (96MHz)Pin-to-Pin LQFP-48 (96MHz) — direct hardware replacement, register-compatible with STM32F1.

Technical Frequently Asked Questions (FAQ) — STM32F103RCT6 (LQFP-64(10x10))

Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formats
IPC-7351B / IEEE-315

What is the Pinout and operating voltage specification of STM32F103RCT6 (LQFP-64(10x10))?

Manufactured by ST, the STM32F103RCT6 is housed in a LQFP-64(10x10) package with 64 pins and a 0.50 mm lead pitch. Key pins include: 1 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))), 2 (PC13TAMPER - - RTC: Multiplexed I/O & Peripheral Pin PC13TAMPER - - RTC (RTC/CLK)), 3 (PC14 - OSC32 IN(5)_: Multiplexed I/O & Peripheral Pin PC14 - OSC32 IN(5)_ (RTC/CLK)), 4 (PC15 - OSC32 OUT(5)_: Multiplexed I/O & Peripheral Pin PC15 - OSC32 OUT(5)_ (RTC/CLK)), 5 (PD0: Multiplexed I/O & Peripheral Pin PD0 (RTC/CLK)), 6 (PD1: Multiplexed I/O & Peripheral Pin PD1 (RTC/CLK)).

What are the IPC-7351B PCB Footprint dimensions for STM32F103RCT6?

Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F103RCT6 (LQFP-64(10x10)) has a nominal body envelope of 10.00 × 10.00 mm, pitch e = 0.50 mm, and 64 copper pads.

Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F103RCT6?

You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F103RCT6 (ST, LQFP-64(10x10)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.

Static Reference Appendix: Pinout Table (64 pins) & STM32F103 Family VariantsExpand static table
Pin #Signal NameElectrical TypeFunctional Description & Design Notes
1VBATPower_InPrimary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
2PC13TAMPER - - RTCDigital_IOSignal terminal PC13TAMPER - - RTC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13TAMPER - - RTC. Supported peripheral buses: RTC/CLK.
3PC14 - OSC32 IN(5)_Digital_IOSignal terminal PC14 - OSC32 IN(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14 - OSC32 IN(5)_. Supported peripheral buses: RTC/CLK.
4PC15 - OSC32 OUT(5)_Digital_IOSignal terminal PC15 - OSC32 OUT(5)_ (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15 - OSC32 OUT(5)_. Supported peripheral buses: RTC/CLK.
5PD0Digital_IOSignal terminal PD0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD0. Supported peripheral buses: RTC/CLK.
6PD1Digital_IOSignal terminal PD1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD1. Supported peripheral buses: RTC/CLK.
7NRSTDigital_IOActive-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals.
8PC0Digital_IOSignal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC.
9PC1Digital_IOSignal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC.
10PC2Digital_IOSignal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC.
11PC3Digital_IOSignal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC.
12VSSAGND0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks.
13VDDAPower_InPrimary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
14PA0WKUP -Digital_IOSignal terminal PA0WKUP - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0WKUP -. Supported peripheral buses: UART, ADC, PWM.
15PA1Digital_IOSignal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC.
16PA2Digital_IOSignal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC, PWM.
17PA3Digital_IOSignal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, PWM.
18VSS_4GND0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks.
19VDD_4Power_InPrimary positive power supply input (VDD_4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
20PA4Digital_IOSignal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, ADC, DAC.
21PA5Digital_IOSignal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, DAC.
22PA6Digital_IOSignal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC.
23PA7Digital_IOSignal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC.
24PC4Digital_IOSignal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC.
25PC5Digital_IOSignal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC.
26PB0Digital_IOSignal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC, PWM.
27PB1Digital_IOSignal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC, PWM.
28PB2Digital_IOSignal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General.
29PB10Digital_IOSignal terminal PB10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SCL. Supported peripheral buses: UART, I2C.
30PB11Digital_IOSignal terminal PB11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C2_SDA. Supported peripheral buses: UART, I2C.
31VSS_1GND0V electrical ground return terminal (VSS_1) for internal core logic, I/O drivers, and analog sub-blocks.
32VDD_1Power_InPrimary positive power supply input (VDD_1) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
33PB12Digital_IOSignal terminal PB12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_NSS, I2C2_SMBA. Supported peripheral buses: UART, SPI, I2C.
34PB13Digital_IOSignal terminal PB13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_SCK. Supported peripheral buses: UART, SPI, PWM.
35PB14Digital_IOSignal terminal PB14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MISO. Supported peripheral buses: UART, SPI, PWM.
36PB15Digital_IOSignal terminal PB15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI2_MOSI. Supported peripheral buses: SPI.
37PC6Digital_IOSignal terminal PC6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC6. Supported peripheral buses: General.
38PC7Digital_IOSignal terminal PC7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC7. Supported peripheral buses: General.
39PC8Digital_IOSignal terminal PC8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC8. Supported peripheral buses: General.
40PC9Digital_IOSignal terminal PC9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC9. Supported peripheral buses: General.
41PA8Digital_IOSignal terminal PA8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA8. Supported peripheral buses: UART, RTC/CLK.
42PA9Digital_IOSignal terminal PA9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA9. Supported peripheral buses: UART.
43PA10Digital_IOSignal terminal PA10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA10. Supported peripheral buses: UART.
44PA11Digital_IOSignal terminal PA11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA11. Supported peripheral buses: USB, UART, CAN.
45PA12Digital_IOSignal terminal PA12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA12. Supported peripheral buses: USB, UART, CAN.
46PA13Digital_IOSignal terminal PA13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA13. Supported peripheral buses: SWD/JTAG.
47VSS_2GND0V electrical ground return terminal (VSS_2) for internal core logic, I/O drivers, and analog sub-blocks.
48VDD_2Power_InPrimary positive power supply input (VDD_2) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
49PA14Digital_IOSignal terminal PA14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA14. Supported peripheral buses: SWD/JTAG.
50PA15Digital_IOSignal terminal PA15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_NSS. Supported peripheral buses: SPI, SWD/JTAG.
51PC10Digital_IOSignal terminal PC10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC10. Supported peripheral buses: UART.
52PC11Digital_IOSignal terminal PC11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC11. Supported peripheral buses: UART.
53PC12Digital_IOSignal terminal PC12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC12. Supported peripheral buses: UART.
54PD2Digital_IOSignal terminal PD2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PD2. Supported peripheral buses: UART.
55PB3Digital_IOSignal terminal PB3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_SCK. Supported peripheral buses: SPI, SWD/JTAG.
56PB4Digital_IOSignal terminal PB4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI3_MISO. Supported peripheral buses: SPI, SWD/JTAG.
57PB5Digital_IOSignal terminal PB5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SMBA, SPI3_MOSI_. Supported peripheral buses: SPI, I2C.
58PB6Digital_IOSignal terminal PB6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SCL. Supported peripheral buses: I2C.
59PB7Digital_IOSignal terminal PB7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: I2C1_SDA. Supported peripheral buses: I2C.
60BOOT0Digital_IOSignal terminal BOOT0 (I, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: BOOT0. Supported peripheral buses: General.
61PB8Digital_IOSignal terminal PB8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB8. Supported peripheral buses: General.
62PB9Digital_IOSignal terminal PB9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB9. Supported peripheral buses: General.
63VSS_3GND0V electrical ground return terminal (VSS_3) for internal core logic, I/O drivers, and analog sub-blocks.
64VDD_3Power_InPrimary positive power supply input (VDD_3) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V).
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