Mechanical Dimensions & Land Pattern (LQFP-144(20x20))
Extracted from Datasheet & IPC-7351B NormalizedPackage Body (D × E)Nominal
20.00 × 20.00 mm
Height (A) & Pitch (e)IPC-7351B
A=1.60mm · e=0.50mm
Pad Size (W × L)Level B
0.27 × 1.30 mm
Pins / Total PadsTopology
144P / 144Pad (QUAD_ROW)
Recommended Companion BOM & Drop-In Equivalents
Passive external components per reference schematic and 1:1 pin-compatible alternatives| Designator / Replacement MPN | Value / Package | Function & PCB Layout Rule |
|---|---|---|
| N/A BOM | Per application circuit LQFP-144(20x20) | Size power & signal trace widths for rated load current following IPC-2221 clearance rules. |
Technical Frequently Asked Questions (FAQ) — STM32F101ZDT6 (LQFP-144(20x20))
Quick answers covering Pinout, IPC-7351B Land Pattern dimensions, and CAD export formatsWhat is the Pinout and operating voltage specification of STM32F101ZDT6 (LQFP-144(20x20))?
Manufactured by ST, the STM32F101ZDT6 is housed in a LQFP-144(20x20) package with 144 pins and a 0.50 mm lead pitch. Key pins include: 1 (PE2: Multiplexed I/O & Peripheral Pin PE2 (General)), 2 (PE3: Multiplexed I/O & Peripheral Pin PE3 (General)), 3 (PE4: Multiplexed I/O & Peripheral Pin PE4 (General)), 4 (PE5: Multiplexed I/O & Peripheral Pin PE5 (General)), 5 (PE6: Multiplexed I/O & Peripheral Pin PE6 (General)), 6 (VBAT: Power Supply Input (VBAT — 3.3V VDD (Max 4.0V))).
What are the IPC-7351B PCB Footprint dimensions for STM32F101ZDT6?
Normalized from the official datasheet mechanical drawing per IPC-7351B (Density Level B Nominal), STM32F101ZDT6 (LQFP-144(20x20)) has a nominal body envelope of 20.00 × 20.00 mm, pitch e = 0.50 mm, and 144 copper pads.
Where can I download KiCad (.kicad_mod, .kicad_sym), Fusion 360 (.lbr), and 3D STEP models for STM32F101ZDT6?
You can download the verified open-hardware (CERN-OHL-P-2.0) CAD library bundle for STM32F101ZDT6 (ST, LQFP-144(20x20)) directly on this page, including KiCad 8 Footprints (.kicad_mod), Schematic Symbols (.kicad_sym), Autodesk Fusion 360 / Eagle (.lbr), and 3D STEP AP214 / WebGL GLB models.
Static Reference Appendix: Pinout Table (144 pins) & STM32F101 Family VariantsExpand static table
| Pin # | Signal Name | Electrical Type | Functional Description & Design Notes |
|---|---|---|---|
| 1 | PE2 | Digital_IO | Signal terminal PE2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE2. Supported peripheral buses: General. |
| 2 | PE3 | Digital_IO | Signal terminal PE3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE3. Supported peripheral buses: General. |
| 3 | PE4 | Digital_IO | Signal terminal PE4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE4. Supported peripheral buses: General. |
| 4 | PE5 | Digital_IO | Signal terminal PE5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE5. Supported peripheral buses: General. |
| 5 | PE6 | Digital_IO | Signal terminal PE6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE6. Supported peripheral buses: General. |
| 6 | VBAT | Power_In | Primary positive power supply input (VBAT) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 7 | PC13-TAMPER-RTC | Digital_IO | Signal terminal PC13-TAMPER-RTC (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC13-TAMPER-RTC. Supported peripheral buses: RTC/CLK. |
| 8 | PC14-OSC32_IN | Digital_IO | Signal terminal PC14-OSC32_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC14-OSC32_IN. Supported peripheral buses: RTC/CLK. |
| 9 | PC15-OSC32_OUT | Digital_IO | Signal terminal PC15-OSC32_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC15-OSC32_OUT. Supported peripheral buses: RTC/CLK. |
| 10 | PF0 | Digital_IO | Signal terminal PF0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF0. Supported peripheral buses: General. |
| 11 | PF1 | Digital_IO | Signal terminal PF1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF1. Supported peripheral buses: General. |
| 12 | PF2 | Digital_IO | Signal terminal PF2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF2. Supported peripheral buses: General. |
| 13 | PF3 | Digital_IO | Signal terminal PF3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF3. Supported peripheral buses: General. |
| 14 | PF4 | Digital_IO | Signal terminal PF4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF4. Supported peripheral buses: General. |
| 15 | PF5 | Digital_IO | Signal terminal PF5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF5. Supported peripheral buses: General. |
| 16 | VSS_5 | GND | 0V electrical ground return terminal (VSS_5) for internal core logic, I/O drivers, and analog sub-blocks. |
| 17 | VDD_5 | Power_In | Primary positive power supply input (VDD_5) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 18 | PF6 | Digital_IO | Signal terminal PF6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF6. Supported peripheral buses: General. |
| 19 | PF7 | Digital_IO | Signal terminal PF7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF7. Supported peripheral buses: General. |
| 20 | PF8 | Digital_IO | Signal terminal PF8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF8. Supported peripheral buses: General. |
| 21 | PF9 | Digital_IO | Signal terminal PF9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF9. Supported peripheral buses: General. |
| 22 | PF10 | Digital_IO | Signal terminal PF10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF10. Supported peripheral buses: General. |
| 23 | OSC_IN | Digital_IO | Signal terminal OSC_IN (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_IN. Supported peripheral buses: RTC/CLK. |
| 24 | OSC_OUT | Digital_IO | Signal terminal OSC_OUT (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: OSC_OUT. Supported peripheral buses: RTC/CLK. |
| 25 | NRST | Digital_IO | Active-low hardware reset terminal (NRST): pulling this pin Low resets the processor core and peripherals. |
| 26 | PC0 | Digital_IO | Signal terminal PC0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC0. Supported peripheral buses: ADC. |
| 27 | PC1 | Digital_IO | Signal terminal PC1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC1. Supported peripheral buses: ADC. |
| 28 | PC2 | Digital_IO | Signal terminal PC2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC2. Supported peripheral buses: ADC. |
| 29 | PC3 | Digital_IO | Signal terminal PC3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC3. Supported peripheral buses: ADC. |
| 30 | VSSA | GND | 0V electrical ground return terminal (VSSA) for internal core logic, I/O drivers, and analog sub-blocks. |
| 31 | VREF- | Analog | Signal terminal VREF- (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF-. Supported peripheral buses: General. |
| 32 | VREF+ | Analog | Signal terminal VREF+ (Analog, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: VREF+. Supported peripheral buses: General. |
| 33 | VDDA | Power_In | Primary positive power supply input (VDDA) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 34 | PA0WKUP - | Digital_IO | Signal terminal PA0WKUP - (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA0WKUP -. Supported peripheral buses: UART, ADC. |
| 35 | PA1 | Digital_IO | Signal terminal PA1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA1. Supported peripheral buses: UART, ADC, PWM. |
| 36 | PA2 | Digital_IO | Signal terminal PA2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA2. Supported peripheral buses: UART, ADC. |
| 37 | PA3 | Digital_IO | Signal terminal PA3 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PA3. Supported peripheral buses: UART, ADC. |
| 38 | VSS_4 | GND | 0V electrical ground return terminal (VSS_4) for internal core logic, I/O drivers, and analog sub-blocks. |
| 39 | VDD_4 | Power_In | Primary positive power supply input (VDD_4) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 40 | PA4 | Digital_IO | Signal terminal PA4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_NSS. Supported peripheral buses: SPI, DAC. |
| 41 | PA5 | Digital_IO | Signal terminal PA5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_SCK. Supported peripheral buses: SPI, ADC, DAC. |
| 42 | PA6 | Digital_IO | Signal terminal PA6 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MISO. Supported peripheral buses: SPI, ADC. |
| 43 | PA7 | Digital_IO | Signal terminal PA7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: SPI1_MOSI. Supported peripheral buses: SPI, ADC. |
| 44 | PC4 | Digital_IO | Signal terminal PC4 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC4. Supported peripheral buses: ADC. |
| 45 | PC5 | Digital_IO | Signal terminal PC5 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PC5. Supported peripheral buses: ADC. |
| 46 | PB0 | Digital_IO | Signal terminal PB0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB0. Supported peripheral buses: ADC. |
| 47 | PB1 | Digital_IO | Signal terminal PB1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB1. Supported peripheral buses: ADC. |
| 48 | PB2 | Digital_IO | Signal terminal PB2 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PB2. Supported peripheral buses: General. |
| 49 | PF11 | Digital_IO | Signal terminal PF11 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF11. Supported peripheral buses: General. |
| 50 | PF12 | Digital_IO | Signal terminal PF12 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF12. Supported peripheral buses: General. |
| 51 | VSS_6 | GND | 0V electrical ground return terminal (VSS_6) for internal core logic, I/O drivers, and analog sub-blocks. |
| 52 | VDD_6 | Power_In | Primary positive power supply input (VDD_6) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 53 | PF13 | Digital_IO | Signal terminal PF13 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF13. Supported peripheral buses: General. |
| 54 | PF14 | Digital_IO | Signal terminal PF14 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF14. Supported peripheral buses: General. |
| 55 | PF15 | Digital_IO | Signal terminal PF15 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PF15. Supported peripheral buses: General. |
| 56 | PG0 | Digital_IO | Signal terminal PG0 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG0. Supported peripheral buses: General. |
| 57 | PG1 | Digital_IO | Signal terminal PG1 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PG1. Supported peripheral buses: General. |
| 58 | PE7 | Digital_IO | Signal terminal PE7 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE7. Supported peripheral buses: General. |
| 59 | PE8 | Digital_IO | Signal terminal PE8 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE8. Supported peripheral buses: General. |
| 60 | PE9 | Digital_IO | Signal terminal PE9 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE9. Supported peripheral buses: General. |
| 61 | VSS_7 | GND | 0V electrical ground return terminal (VSS_7) for internal core logic, I/O drivers, and analog sub-blocks. |
| 62 | VDD_7 | Power_In | Primary positive power supply input (VDD_7) operating in the 3.3V VDD (Max 4.0V) domain (Max rating: 4.0V). |
| 63 | PE10 | Digital_IO | Signal terminal PE10 (I/O, 3.3V VDD (Max 4.0V) domain). Multiplexed alternate functions: PE10. Supported peripheral buses: General. |
| 64 | IO64 | Digital_IO | General Purpose Digital I/O Pin IO64 |